DMA asynchronous mode clock stretch

Claim 1

In a microprocessor controlled data processing system including a bus for data, address and control signals, a system clock, an asynchronous microprocessor which generates a valid data control signal to indicate that valid data is on the bus and responds to a data transfer acknowledgment signal to regulate the length of a data transfer, a dynamic random access memory which provides a refresh signal while data is being refreshed in the memory, and I/O device running asynchronously of the memory, and direct memory access control means for bypassing the microprocessor in the transferring of data between the memory and the I/O device during a repetitively recurring fixed length transfer window signal generated by said direct memory access control means from a cyclical timing signal of the system clock, the improvement comprising: data transfer acknowledgment means having gate means responsive to said refresh signal, said transfer window signal and said valid data control signal for inhibiting the generation of a transfer acknowledgment signal while the memory is being refreshed or until valid data is available, logic means responsive to the generation of said transfer acknowledgment signal for extending the length of said transfer window signal to permit completion of the data transfer when the occurrence of said refresh period or late availability of valid data prevents completion of a data transfer during a transfer window signal of normal length.