US4608554A
Expired / Lapsed
US
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Asynchronous parallel fixed point converter
Assignee: Mobil Oil AS
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Filing: 1982-09-14
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Granted: 1986-08-26
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Expires: 2002-09-14
Abstract
Abstract An electronic circuit is used as an asynchronous floating point converter to process data. Data words are received and processed by the floating point converter to produce processed output data. The function for processing is software selectable and may be accomplished rapidly since the electronic circuit is not a clocked device.
Inventors
- 👤 Ron B. Blair
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 15:58
CPC Classifications
G; G06; G06F; G06F5/00; G06F5/01; G06F5/012; H; H03; H03M; H03M7/00; H03M7/14; H03M7/24
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
126 words
In a high speed data processing system having a host computer wherein fixed point parallel digital data is converted to floating point parallel digital data, a software configurable electronic circuit comprising: slave means connected to said host computer for receiving control signals; means connected to said slave means for delaying a control signal a predetermined time; receiver means connected to said computer for receiving fixed point parallel digital data; shift means connected to said receiver means for shifting said fixed point parallel digital data asynchronously; calculate means connected to said shift means for simultaneously calculating an exponent due to a shift in said parallel digital data; and output means connected to said calculate means for providing an output of said shifted digital data with said exponent.
Claim 2
Dependent Claim
126 words
In a high speed data processing system having a host computer wherein fixed point parallel digital data is converted to floating point parallel digital data, a software configurable electronic circuit comprising: slave means connected to said host computer for receiving control signals; means connected to said slave means for delaying a control signal a predetermined time; receiver means connected to said computer for receiving fixed point parallel digital data; shift means connected to said receiver means for shifting said fixed point parallel digital data asynchronously; calculate means connected to said shift means for simultaneously calculating an exponent due to a shift in said parallel digital data; and output means connected to said calculate means for providing an output of said shifted digital data with said exponent.
Claim 3
Dependent Claim
15 words
The circuit according to claim 1 wherein said receiver means include a 2's complement converter.
Claim 4
Dependent Claim
18 words
The circuit according to claim 1 also including means for bypassing said shift means and said calculate means.
Claim 5
Dependent Claim
103 words
An asynchronous floating point parallel digital data converter for use between a central processing unit and a mass memory comprising: first means connected to the central processing unit for receiving fixed point parallel digital data; second means connected to said first means for performing a 2's complement conversion on said fixed point parallel digital data; third means connected to said second means for shifting said 2's complement converted fixed point parallel digital data; fourth means for simultaneously calculating an exponent due to said shift; and fifth means connected to said memory for providing an output of said shifted digital data with said exponent.
Claim 6
Dependent Claim
103 words
An asynchronous floating point parallel digital data converter for use between a central processing unit and a mass memory comprising: first means connected to the central processing unit for receiving fixed point parallel digital data; second means connected to said first means for performing a 2's complement conversion on said fixed point parallel digital data; third means connected to said second means for shifting said 2's complement converted fixed point parallel digital data; fourth means for simultaneously calculating an exponent due to said shift; and fifth means connected to said memory for providing an output of said shifted digital data with said exponent.
Claim 7
Dependent Claim
31 words
The floating point converter according to claim 4 also including: connection between said central processing unit and said memory for bypassing said second means, said third means, and said fourth means.
References Cited (Backward Citations)
US3742198A
Cited
US4305063A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-08-25 | 1990-02-24 | 1990-08-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-08-25 | 1994-02-24 | 1994-08-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-08-25 | 1998-02-24 | 1998-08-26 | $7700.00 | Window Closed / Lapsed |