Interface circuit for interconnecting peripherals to an information processing device

Claim 1

An interface circuit for an information processing system comprising: a data buss; a plurality of information processing units; a plurality of buffer circuits, each connecting an associated one of said information processing units to said data buss; a plurality of power sources, each associated with and supplying power to one of said information processing units and its associated said buffer circuit; a common power supply line interconnecting all of said plurality of power sources, said power supply line bidirectionally supplying power from any one of said plurality of power sources to all of said buffer circuits; a plurality of buffer enable means, each associated with a said buffer circuit, for monitoring the associated said power source and enabling said buffer to transfer information between said data buss and said associated information processing unit when said associated power source is supplying power thereto; each said buffer circuit being thereby disabled when adequate power is not supplied to its said associated information processing unit by the associated said power source while remaining powered to thereby develop a high input impedance.