Transversal filter equalizer with minimally interactive adjustments

Claim 2

Apparatus for providing amplitude and/or phase equalization of a channel adapted to process a signal, such apparatus comprising: a. means for accepting said signal, and providing therefrom, first, second, and third relatively delayed signals, wherein the delay times of said delayed signals are essentially integer multiples of a unit delay, and said second delayed signal constitutes a reference signal, b. first and second means for algebraically combining the first and third of said delayed signals to produce first and second resultant signals, c. means for combining the first of said resultant signals with said reference signal to produce a substantially d.c. free component signal, d. means for receiving and modifying the amplitude and sign of said component signal to provide a first partial signal to effect amplitude equalization of said channel, e. means for receiving and modifying the amplitude and sign of said second resultant signal to provide a second partial signal to effect phase equalization of said channel, f. means for receiving and modifying the amplitude and sign of said reference signal to provide a third partial signal to effect the absolute level of equalization of said channel, and g. means for combining said first, second and third partial signals to effect overall equalization of said channel.

Claim 3

Apparatus for equalization of amplitude distortion and/or phase distortion in a channel for transmitting a signal, such apparatus comprising: a. means for providing a maximum signal delay of 2n delay units, where n is an integer, said delay means disposed for receiving said signal and providing therefrom delayed versions of said signal, said versions having delays of 0,1,2, . . . 2n of said delay units, b. means for adjusting amplitudes of said delayed signal versions, c. means for receiving a signal pair of said amplitude adjusted delayed signal versions, wherein one signal of said signal pair is delayed by m of said delay units, and the second signal of said signal pair is delayed by 2n-m of said delay units, wherein m equals the integers 0,1,2, . . . n -1, d. means for combining said pair of amplitude adjusted delayed signal versions to provide a signal in phase with said delayed signal version which is delayed by n of said delay units, e. means for combining said pair of amplitude adjusted delayed signal versions to provide a signal orthogonal to said delayed signal version which is delayed by n of said delay units, f. means for adjusting magnitude and sign of said signal version which is delayed by n of said delay units, whereby the absolute level of said equalization is adjusted, g. means for adjusting magnitude and sign of said in-phase signal, whereby the amplitude of said equalization is adjusted, h. means for adjusting the magnitude and sign of said orthogonal signal, whereby the phase of said equalization is adjusted, and i. means for combining said adjusted signal version which is delayed by n of said delay units, said adjusted in-phase signal, and said adjusted orthogonal signal, to effect overall equalization of said channel.

Claim 4

Apparatus for equalization of amplitude distortion and/or phase distortion in a channel for transmitting a signal, such apparatus comprising: a. means for providing a maximum signal delay of 2n delay units, where n is an integer, said delay means disposed for receiving said signal and providing therefrom delayed versions of said signal, said versions having delays of 0,1,2, . . . 2n of said delay units, b. means for adjusting amplitudes of said delayed signal versions, c. means for receiving a signal pair of said amplitude adjusted delayed signal versions, wherein one signal of said signal pair is delayed by m of said delay units, and the second signal of said signal pair is delayed by 2n-m of said delay units, wherein m equals the integers 0,1,2, . . . n -1, d. means for combining said pair of amplitude adjusted delayed signal versions to provide a signal in phase with said delayed signal version which is delayed by n of said delay units, e. means for combining said pair of amplitude adjusted delayed signal versions to provide a signal orthogonal to said delayed signal version which is delayed by n of said delay units, f. means for adjusting magnitude and sign of said signal version which is delayed by n of said delay units, whereby the absolute level of said equalization is adjusted, g. means for adjusting magnitude and sign of said in-phase signal, whereby the amplitude of said equalization is adjusted, h. means for adjusting the magnitude and sign of said orthogonal signal, whereby the phase of said equalization is adjusted, and i. means for combining said adjusted signal version which is delayed by n of said delay units, said adjusted in-phase signal, and said adjusted orthogonal signal, to effect overall equalization of said channel.

Claim 5

The apparatus of claim 2 wherein said delay means is a tapped electrical delay line.

Claim 6

The apparatus of claim 2, wherein a. said means for adjusting amplitudes of said delayed signal versions are attenuators, whereby said delayed signal versions comprising said signal pair are adjusted for equal amplitudes, b. said means for combining said signal pair to provide said in-phase signal is a signal adder, and c. said means for combining said signal pair to provide said orthogonal signal is a signal subtracter.

Claim 7

The apparatus of claim 2, wherein said means for adjusting the magnitude and sign of said in-phase signal, of said orthogonal signal and said signal version which is delayed by n of said delay units, are adjustable multipliers.

Claim 8

Signal equalizing apparatus comprising: a. an array of delay elements disposed to receive said signal, and providing therefrom delayed versions of said signal at equal delay increments from 0 delay to a maximum delay, b. means for receiving said delayed signal version of delay equal to one half of said maximum delay, c. means for receiving a pair of said delayed signal versions, wherein the first signal of said pair is delayed by a fixed number of said delay increments less than said signal version equal to one half of said maximum delay, and the second signal of said pair is delayed by the same number of said delay increments more than said signal version of delay equal to one half of said maximum delay, d. means for adjusting the amplitudes of said delayed signal versions comprising said delayed signal pair, e. means for combining said amplitude adjusted signal pair to provide a signal in phase with said signal version of delay equal to one half of said maximum delay, f. means for combining said amplitude adjusted signal pair to provide a signal orthogonal to said signal version of delay equal to one half of said maximum delay, g. means for cancelling the d.c. component of said in-phase signal to provide a d.c. cancelled in-phase signal, h. means for cancelling the d.c. component of said orthogonal signal to provide a d.c. cancelled orthogonal signal, i. means for adjusting magnitude and sign of said signal version of delay equal to one half of said maximum delay, whereby the absolute level of equalization is adjusted, j. means for adjusting magnitude and sign of said d.c. cancelled in-phase signal, whereby amplitude equalization is adjusted, k. means for adjusting the magnitude and sign of said d.c. cancelled orthogonal signal, whereby phase equalization is adjusted, and l. means for combining said adjusted signal version of delay equal to one-half of said maximum delay, said adjusted d.c. cancelled in-phase signal, and said adjusted d.c. cancelled orthogonal signal, to effect overall signal equalizing by said apparatus.

Claim 9

Signal equalizing apparatus comprising: a. an array of delay elements disposed to receive said signal, and providing therefrom delayed versions of said signal at equal delay increments from 0 delay to a maximum delay, b. means for receiving said delayed signal version of delay equal to one half of said maximum delay, c. means for receiving a pair of said delayed signal versions, wherein the first signal of said pair is delayed by a fixed number of said delay increments less than said signal version equal to one half of said maximum delay, and the second signal of said pair is delayed by the same number of said delay increments more than said signal version of delay equal to one half of said maximum delay, d. means for adjusting the amplitudes of said delayed signal versions comprising said delayed signal pair, e. means for combining said amplitude adjusted signal pair to provide a signal in phase with said signal version of delay equal to one half of said maximum delay, f. means for combining said amplitude adjusted signal pair to provide a signal orthogonal to said signal version of delay equal to one half of said maximum delay, g. means for cancelling the d.c. component of said in-phase signal to provide a d.c. cancelled in-phase signal, h. means for cancelling the d.c. component of said orthogonal signal to provide a d.c. cancelled orthogonal signal, i. means for adjusting magnitude and sign of said signal version of delay equal to one half of said maximum delay, whereby the absolute level of equalization is adjusted, j. means for adjusting magnitude and sign of said d.c. cancelled in-phase signal, whereby amplitude equalization is adjusted, k. means for adjusting the magnitude and sign of said d.c. cancelled orthogonal signal, whereby phase equalization is adjusted, and l. means for combining said adjusted signal version of delay equal to one-half of said maximum delay, said adjusted d.c. cancelled in-phase signal, and said adjusted d.c. cancelled orthogonal signal, to effect overall signal equalizing by said apparatus.

Claim 10

The apparatus of claim 6 wherein said delay means is a tapped electrical delay line.

Claim 11

The apparatus of claim 6, wherein a. said means for adjusting amplitudes of said delayed signal versions are attenuators, whereby said delayed signal versions comprising said signal pair are adjusted for equal amplitudes, b. said means for combining said signal pair to provide said in-phase signal is a signal adder, and c. said means for combining said signal pair to provide said orthogonal signal is a signal subtracter.

Claim 12

The apparatus of claim 6, wherein said means for adjusting the magnitude and sign of said in-phase signal, of said orthogonal signal, and said signal version of delay equal to one half said maximum delay, are adjustable multipliers.

Claim 13

The apparatus of claim 6 wherein said means for cancelling said d.c. components are subtracters.