Linearized phase comparator and phase-locked loop comprising such a phase comparator

Claim 2

In a phase comparator system having first and second inputs for receiving first and second input signals to be compared, and a first output, the system comprising a phase comparator with third and fourth inputs and a second output, means coupling said third and fourth inputs to said first and second inputs respectively and means coupling said second output to said first output; the improvement comprising a dynamic reduction stage comprised of means coupled between said second and fourth inputs for reducing the phase difference between said signals applied to said third and fourth inputs by a determined value, and delay means coupled between said first and second outputs for increasing the output signal at said second output by an amount dependent upon said determined value.

Claim 3

The phase comparator system of claim 1 wherein said dynamic reduction stage further comprises means coupled to said second output for deriving a value signal corresponding to said determined value, said means coupled between said second and fourth inputs comprises a first adder connected to add said value signal to signals applied to said fourth input, and said delay means comprises a delay circuit connected to receive said value signal, and a second adder connected to add the output of said delay circuit to signals applied to said first output.

Claim 4

The phase comparator system of claim 1 wherein said dynamic reduction stage comprises a summing device having a first positive input coupled to said second output, a second negative input coupled to said second output by way of a filter, and a third positive input coupled to the output of said summing device by way of a delay line, said means for reducing phase difference comprising adding means for adding the output of said summing means to signals applied to said fourth input, said means for increasing the output signal comprising delay means for receiving the output of said summing device, and adding means for adding the output of said delay means to signals applied to said first output.

Claim 5

In a phase-locked loop comprising a phase comparator system, a loop filter and an oscillator, means connecting said phase comparator for measuring the phase difference between an input signal and the output signal of the oscillator, said loop filter comprising filtering means connected to convey a signal corresponding to said difference from said comparator to said oscillator; the improvement wherein said phase comparator comprises a phase comparator having a first input for receiving said input signal, a second input and a first output, and a dynamic reduction stage comprising means coupled between said oscillator and second input for reducing the phase difference between signals applied to the inputs of said phase comparator by a determined value, and delay means coupled between said loop filter and said first output for increasing the output signal at said first output by an amount dependent upon said determined value.

Claim 6

In a phase-locked loop comprising a phase comparator system, a loop filter and an oscillator, means connecting said phase comparator for measuring the phase difference between an input signal and the output signal of the oscillator, said loop filter comprising filtering means connected to convey a signal corresponding to said difference from said comparator to said oscillator; the improvement wherein said phase comparator comprises a phase comparator having a first input for receiving said input signal, a second input and a first output, and a dynamic reduction stage comprising means coupled between said oscillator and second input for reducing the phase difference between signals applied to the inputs of said phase comparator by a determined value, and delay means coupled between said loop filter and said first output for increasing the output signal at said first output by an amount dependent upon said determined value.

Claim 7

The phase-locked loop of claim 4 wherein said dynamic reduction stage further comprises means coupled to said second output for deriving a value signal corresponding to said determined value, said means coupled between said second input and oscillator comprises a first adder connected to add said value signal to signals applied to said second input, and said delay means comprises a delay circuit connected to receive said value signal, and a second adder connected to add the output of said delay circuit to signals applied to said first output.

Claim 8

The phase-locked loop of claim 4 wherein said dynamic reduction stage comprises a summing device having a first positive input coupled to the output of said comparator, a second negative input coupled to the output of said comparator by way of a filter, and a third positive input coupled to the output of said summing device by way of a delay line, said means for reducing phase difference comprising adding means for adding the output of said summing means to signals applied to said second input, said means for increasing the output signal comprising delay means for receiving the output of said summing device, and adding means for adding the output of said delay means to signals applied to the output of said comparator.

Claim 9

The phase-locked loop of claim 6 wherein the loop is a closed digital loop and the transfer function of said filter is substantially equal to the transfer function of said loop.

Claim 10

The phase-locked loop of claim 7, wherein said loop filter comprises a microprocessor.