US4607219A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method of inspecting semiconductor non-volatile memory devices
Assignee: NEC Electronics Corp
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Filing: 1983-09-09
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Granted: 1986-08-19
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Expires: 2003-09-09
Abstract
Abstract Memorized data retention characteristics of a FAMOS transistor is tested by writing predetermined information into a semiconductor element while it is in a state of a wafer and the information is read out after the element has been mounted in a package. The written information and the read out information are checked to determine whether they coincide with each other or not.
Inventors
- 👤 Shigekazu Isosaka
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 21:19
CPC Classifications
G; G11; G11C; G11C29/00; G11C29/56
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
109 words
A method of inspecting semiconductor non-volatile memory devices comprising the steps of: preparing a plurality of semiconductor non-volatile memory elements into the form of a semiconductor wafer, writing predetermined information indicative of data retention capability into said semiconductor non-volatile memory elements in said semiconductor wafer, dividing said semiconductor wafer into a plurality of separate semiconductor non-volatile memory elements, housing said semiconductor non-volatile elements in individual packages to complete said semiconductor non-volatile memory devices, then reading information out of the completed semiconductor non-volatile memory devices respectively, checking with respect to the respective non-volatile memory devices whether said written information indicative of data retention capability coincides with said read out information.
Claim 2
Independent Claim
109 words
A method of inspecting semiconductor non-volatile memory devices comprising the steps of: preparing a plurality of semiconductor non-volatile memory elements into the form of a semiconductor wafer, writing predetermined information indicative of data retention capability into said semiconductor non-volatile memory elements in said semiconductor wafer, dividing said semiconductor wafer into a plurality of separate semiconductor non-volatile memory elements, housing said semiconductor non-volatile elements in individual packages to complete said semiconductor non-volatile memory devices, then reading information out of the completed semiconductor non-volatile memory devices respectively, checking with respect to the respective non-volatile memory devices whether said written information indicative of data retention capability coincides with said read out information.
Claim 3
Dependent Claim
44 words
The method as defined in claim 1 wherein each of said semiconductor non-volatile memory elements comprises a plurality of floating-gate avalanche-injection field effect transistors, and presence and absence of an electric charge in each floating gate are used as binary "1" and "0" values.
Claim 4
Independent Claim
110 words
A method of manufacturing semiconductor non-volatile memory devices comprising the steps of preparing a semiconductor wafer, forming a plurality of semiconductor non-volatile memory elements in said wafer, subjecting said wafer to a first electrical test to reject unsatisfactory elements, writing predetermined information in non-rejected elements, dividing said wafer into a plurality of separate semiconductor non-volatile memory elements, housing each element in a package so as to complete said memory device, heat aging the complete memory device, and subjecting the completed memory device to a second electrical test, said second electrical test including reading information out of each semiconductor non-volatile memory element and comparing the read-out information with said predetermined information.
Claim 5
Independent Claim
110 words
A method of manufacturing semiconductor non-volatile memory devices comprising the steps of preparing a semiconductor wafer, forming a plurality of semiconductor non-volatile memory elements in said wafer, subjecting said wafer to a first electrical test to reject unsatisfactory elements, writing predetermined information in non-rejected elements, dividing said wafer into a plurality of separate semiconductor non-volatile memory elements, housing each element in a package so as to complete said memory device, heat aging the complete memory device, and subjecting the completed memory device to a second electrical test, said second electrical test including reading information out of each semiconductor non-volatile memory element and comparing the read-out information with said predetermined information.
Claim 6
Independent Claim
61 words
A method of inspecting a FAMOS (floating-gate avalanche-injection metal oxide) semiconductor having a floating gate, comprising the steps of: writing information into said FAMOS by supplying an electrical charge to the floating gate; housing said FAMOS; heat aging the FAMOS; reading information of the heat aged FAMOS; and checking the read information to determine if it coincides with the written information.
Claim 7
Independent Claim
61 words
A method of inspecting a FAMOS (floating-gate avalanche-injection metal oxide) semiconductor having a floating gate, comprising the steps of: writing information into said FAMOS by supplying an electrical charge to the floating gate; housing said FAMOS; heat aging the FAMOS; reading information of the heat aged FAMOS; and checking the read information to determine if it coincides with the written information.
References Cited (Backward Citations)
US4379259A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-08-18 | 1990-02-17 | 1990-08-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-08-18 | 1994-02-17 | 1994-08-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-08-18 | 1998-02-17 | 1998-08-19 | $7700.00 | Window Closed / Lapsed |