US4606057A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Arrangement for checking the counting function of counters
Assignee: US Philips Corp
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Filing: 1984-07-19
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Granted: 1986-08-12
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Expires: 2004-07-19
Abstract
Abstract The isochronism of binary counters can be checked by comparing the counting positions. If in a system two counters are required which are operated isochronously but not in synchronism, for example the individual read and write counters for memory addressing purposes, the arrangement according to the invention provides a simple solution by using one counter as a duplicate of the other one instead of duplicating both counters. The parity of the counting position after each increment of both counters is generated. The parity bit of the counter having the highest counting position is delayed by means of a shift register over a number of positions corresponding to the difference in counting positions between the two counters and is then compared with the parity of the counting position of the other counter.
Inventors
- 👤 Johannes van Baardewijk
- 👤 Johan E. A. Hartman
- 👤 Nicolaas Bohlmeyer
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-10 02:32
CPC Classifications
H; H03; H03K; H03K21/00; H03K21/40
Claims Analysis
Total Claims: 2
Claim 1
Independent Claim
235 words
A logical subsystem for checking the counting function of a number of counters n, where (n≧2), which counters are operated isochronously, comprising: a number n of counters, where n≧2; a number n of parity generators, where n≧2; each of said parity generators being connected to one of said counters and each of said counters being connected to one of said parity generators; each of said parity generators having means for generating the parity of the instantaneous counting position of the counter to which it is connected; (n-1) of said parity generators being connected to counters having the highest counting positions; (n-1) shift registers being connected to said n-1 parity generators, such that each of said shift registers shifts the parity of the parity generator to which it is connected by a number of positions corresponding to the difference between the counting position of the counter to which it is connected and the counting position of the counter having the lowest counting position; the output of each of said (n-1) shift registers, and the output of the parity generator connected to said counter having the lowest counting position being connected to a logic circuit such that said logic circuit outputs a first signal if the same parity is presented to all its inputs, and outputs a second signal if the parity presented to one input differs from the parity presented to at least one other input.
Claim 2
Dependent Claim
235 words
A logical subsystem for checking the counting function of a number of counters n, where (n≧2), which counters are operated isochronously, comprising: a number n of counters, where n≧2; a number n of parity generators, where n≧2; each of said parity generators being connected to one of said counters and each of said counters being connected to one of said parity generators; each of said parity generators having means for generating the parity of the instantaneous counting position of the counter to which it is connected; (n-1) of said parity generators being connected to counters having the highest counting positions; (n-1) shift registers being connected to said n-1 parity generators, such that each of said shift registers shifts the parity of the parity generator to which it is connected by a number of positions corresponding to the difference between the counting position of the counter to which it is connected and the counting position of the counter having the lowest counting position; the output of each of said (n-1) shift registers, and the output of the parity generator connected to said counter having the lowest counting position being connected to a logic circuit such that said logic circuit outputs a first signal if the same parity is presented to all its inputs, and outputs a second signal if the parity presented to one input differs from the parity presented to at least one other input.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-08-11 | 1990-02-10 | 1990-08-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-08-11 | 1994-02-10 | 1994-08-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-08-11 | 1998-02-10 | 1998-08-12 | $7700.00 | Window Closed / Lapsed |