Differential pair amplifier enhancement circuit

Claim 2

An enhanced differential pair amplifier circuit comprising: first and second common lines, said first common line being at a different potential than said second common line; first and second input transistors, each input transistor having a base, emitter, and collector, at least one of said bases being provided to receive a voltage input signal; first and second current sources, said first current source connected between the emitter of said first input transistor and first common line, said second current source being connected between the emitter of said second transistor and first common line; a gain-defining emitter degeneration transistor resistor connected between the emitters of said first and second transistors; first and second diode means for linearity compensation, each diode means having first and second ends, said first end of said first diode means being connected to the collector of said first input transistor and said first end of said second diode means being connected to the collector of said second input transistor, said second ends of said first and second diode means being connected to said second common line such that said diode means are forward biased; wherein each of said diode means comprises n diodes, where n is the integral gain of the amplifier; and output signal means for taking an output signal from the collectors of said first and second input transistors.

Claim 3

An enhanced differential pair amplifier circuit as recited in claim 1, wherein: said first end of said diode means is the cathode side of said diode means, and said second end of said diode means is the anode side of the said diode so that the diode means is forward biased during operation of the amplifier.

Claim 4

An enhanced differential pair amplifier circuit as recited in claim 1 wherein each of said diode means comprises n compensation transistors, where n is the integral gain of the amplifier, and where each compensation transistor acts as a diode.

Claim 5

An enhanced differential pair amplifier as recited in claim 3, further comprising: thermal compensation means for correcting for thermally induced nonlinearities in the output with respect to the input of said amplifier.

Claim 6

An enhanced differential pair amplifier circuit as recited in claim 4, said circuit being connected in cascode configuration, wherein said thermal compensation means comprises: first and second thermal compensation transistors, each thermal compensation transistor having first and second ends, said first end of said first thermal compensation transistor being connected to the second end of said first diode means, said first end of said second thermal compensation transistor being connected to the second end of said second diode means, said second ends of said first and second thermal compensation transistors being connected to said second common line; and a voltage source connected between the bases of said first and second thermal compensating transistors to provide a voltage across said first and second thermal compensating transistors approximately equal to the voltage across said first and second diode means multiplied by the gain of said amplifier to provide a multiplied thermal characteristic at the output to correct for thermal characteristics of said first and second diode means.

Claim 7

An enhanced differential pair amplifier circuit as recited in claim 3, wherein: said input and compensation transistors have identical base-to-emitter current versus voltage characteristics.

Claim 8

An enhanced differential pair amplifier circuit as recited in claim 1, wherein: said diode means have substantially identical current versus voltage characteristics as the base-to-emitter voltage characteristics of said input transistors.

Claim 9

An enhanced differential pair amplifier circuit as recited in claim 1, further including: first and second load resistors, said first load resistor being connected in series with said first diode means, and said second load resistor being connected in series with said second diode means.

Claim 10

An enhanced differential pair amplifier as recited in claim 1, further including: switch means for connecting and disconnecting said plurality of diodes in said first and second diode means, said switch means connecting "X" diodes to said first and second input transistors such that X divided by the number of said input transistors used in said differential amplifier circuit equals the gain of said amplifier.

Claim 11

An enhanced differential pair amplifier circuit comprising: first and second common lines, said first common line being at a differential potential than said second common line; first and second input transistors, each input transistor having a base, emitter, and collector, at least one of said bases being provided to receive a voltage input signal; first and second current sources, said first current source connected between the emitter of said first input transistor and first common line, said second current source being connected between the emitter of said second input transistor and first common line; a gain defining emitter degeneration transistor resistor connected between the emitters of said first and second transistors; first and second diode means for linearity compensation, each diode means having first and second ends, said first end of said first diode means being connected to the collector of said first input transistor and said first end of said second diode means being connected to the collector of said second input transistor, said second ends of said first and second diode means being connected to said second common line such that said diode means are forward biased; noninteger compensation means for compensating for nonlinearities of said output signal with respect to said input signal caused by imbalances in the base-to-emitter characteristics of said differential pair when the gain of said amplifier is a noninteger; and output signal means for taking an output signal from the collectors of said first and second input transistors.

Claim 12

An enhanced differential pair amplifier circuit comprising: first and second common lines, said first common line being at a differential potential than said second common line; first and second input transistors, each input transistor having a base, emitter, and collector, at least one of said bases being provided to receive a voltage input signal; first and second current sources, said first current source connected between the emitter of said first input transistor and first common line, said second current source being connected between the emitter of said second input transistor and first common line; a gain defining emitter degeneration transistor resistor connected between the emitters of said first and second transistors; first and second diode means for linearity compensation, each diode means having first and second ends, said first end of said first diode means being connected to the collector of said first input transistor and said first end of said second diode means being connected to the collector of said second input transistor, said second ends of said first and second diode means being connected to said second common line such that said diode means are forward biased; noninteger compensation means for compensating for nonlinearities of said output signal with respect to said input signal caused by imbalances in the base-to-emitter characteristics of said differential pair when the gain of said amplifier is a noninteger; and output signal means for taking an output signal from the collectors of said first and second input transistors.

Claim 13

An enhanced differential pair amplifier as recited in claim 10, wherein said noninteger compensation means further includes: third and fourth current sources, said third current source being connected to said amplifier between said first input transistor and said first diode means, said fourth current source being connected to said amplifier between said second input transistor and said second diode means.