US4605890A
Expired / Lapsed
US
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Synchro power amplifier and control circuit for automatically tuning an inductive load
Assignee: Vernitron Corp
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Filing: 1985-06-24
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Granted: 1986-08-12
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Expires: 2005-06-24
Abstract
Abstract A synchro power amplifier and control circuit for an inductive load has a plurality of synchro leg amplifiers connected to the load. Each amplifier has an interstage transformer for deriving samples of current drawn by the load. A multiplicity of capacitors are respectively connectable in parallel with the (load) upstream of the amplifiers by switches in a circuit 10 responsive to the voltage/current phase angle of the power driving the load, to compensate for the inductance of the load.
Inventors
- 👤 Dennis F. Ogle
- 👤 Charles A. Clark, Jr.
- 👤 Ramon H. Aires
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 22:24
CPC Classifications
H; H02; H02J; H02J3/00; H02J3/18; H02J3/1821; H02J3/1828; Y; Y02; Y02E; Y02E40/00; Y02E40/30
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
102 words
A power amplifier control circuit for an inductive load driven by a plurality of synchro AC inputs, comprising: a plurality of leg amplifiers respectively connected between said AC inputs and said load, each of said amplifiers having circuit means for deriving current samples drawn only by said load from said amplifiers; a multiplicity of capacitors respectively connectable in parallel with said load upstream of said amplifiers; and a plurality of switches connected respectively in circuit with said capacitors for selecting one of said capacitors and for connecting said selected capacitor in parallel with said load to compensate for inductance of said load.
Claim 2
Dependent Claim
102 words
A power amplifier control circuit for an inductive load driven by a plurality of synchro AC inputs, comprising: a plurality of leg amplifiers respectively connected between said AC inputs and said load, each of said amplifiers having circuit means for deriving current samples drawn only by said load from said amplifiers; a multiplicity of capacitors respectively connectable in parallel with said load upstream of said amplifiers; and a plurality of switches connected respectively in circuit with said capacitors for selecting one of said capacitors and for connecting said selected capacitor in parallel with said load to compensate for inductance of said load.
Claim 3
Dependent Claim
23 words
A power amplifier control circuit as defined in claim 1, wherein each of said circuit means for sampling current comprises an interstage transformer.
Claim 4
Dependent Claim
69 words
A power amplifier control circuit as defined in claim 1, further comprising: a reset pulse generator arranged to generate a reset pulse cycle of predetermined time duration; and clamping means connected between said reset pulse generator and each input of each of said leg amplifiers, and operative to command to zero voltage each of said leg amplifiers for said predetermined time duration when said reset pulse is applied thereto.
Claim 5
Dependent Claim
110 words
A power amplifier control circuit as defined in claim 3, further comprising: rectifier means connected to said circuit means for rectifying said current samples; a plurality of comparators having first and second inputs, said rectifier means being connected to said first inputs of said comparators; a plurality of reference current sources of different current levels respectively connected to said second inputs of said comparators, said comparators being effective to compare a larger one of said rectified current samples with said reference currents; and gates connected between said comparators and said switches for connecting one of said capacitors in parallel with said load to compensate for said inductance of said load.
Claim 6
Dependent Claim
136 words
A power amplifier control circuit as defined in claim 4, further comprising: another comparator having two inputs and an output; a resistor-capacitor filter having a predetermined time constant and connected in circuit with said rectifier means and one input of said other comparator, for applying to said other comparator a peak voltage proportional to the largest current passed by any one of said leg amplifiers; and a source of reference voltage connected to the other input of said other comparator, so that said other comparator compares said reference voltage with said peak voltage, said output of said other comparator being connected to said reset pulse generator to apply thereto a reinitiate reset voltage pulse if said peak voltage exceeds said reference voltage for a short time determined by said time constant to reinitiate said reset cycle.
Claim 7
Dependent Claim
85 words
A power amplifier control circuit as defined in claim 4, further comprising: first square pulse generating means connected to said circuit means for generating first square pulses corresponding to said current samples; second square pulse generating means connected to said AC inputs for generating second square pulses corresponding to voltages applied by said amplifiers to said load; and pulse selection gates connected to said first and second square pulse generating means for measuring phase angles between the current and the voltage applied to said load.
Claim 8
Dependent Claim
44 words
A power amplifier control circuit as defined in claim 6, further comprising voltage comparator means connected between said pulse selection gates and said first named gates for applying a go-ahead signal to said first named gates to operate a selected one of said switches.
Claim 9
Dependent Claim
46 words
A power amplifier control circuit as defined in claim 7, wherein said reset pulse generator is connected to said pulse selection gates to apply an overriding pulse thereto for preventing application of said go ahead signal to said first named gates during said reset pulse cycle.
Claim 10
Dependent Claim
41 words
A power amplifier control circuit as defined in claim 4, further comprising relay means in circuit with said reference current sources and connected to said rest pulse generator for cutting off said reference currents when said reset pulse is being generated.
References Cited (Backward Citations)
US3419792A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-08-11 | 1990-02-10 | 1990-08-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-08-11 | 1994-02-10 | 1994-08-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-08-11 | 1998-02-10 | 1998-08-12 | $7700.00 | Window Closed / Lapsed |