US4604729A
Expired / Lapsed
US
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Static-type semiconductor memory device
Assignee: Fujitsu Ltd
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Filing: 1983-04-05
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Granted: 1986-08-05
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Expires: 2003-04-05
Abstract
Abstract A static-type semiconductor memory device having a holding-current controlling circuit such that the holding current supplied to an unselected-state memory block or memory chip is greater than the holding current supplied to a selected-state memory block or memory chip. The current supplied to the peripheral circuit for the unselected-state memory block or memory chip is smaller than the current supplied to the peripheral circuit for the selected-state memory block or memory chip, whereby destruction of stored data can be prevented.
Inventors
- 👤 Masayoshi Kimoto
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 06:19
CPC Classifications
G; G11; G11C; G11C5/00; G11C5/005; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/41; G11C11/413; G11C11/414; G11C11/416
Claims Analysis
Total Claims: 20
Claim 1
Independent Claim
282 words
A static-type semiconductor memory device comprising: a plurality of memory blocks, arranged in rows and columns to form a matrix, having selected and unselected states, any one row of the memory blocks being selected to carry out a reading or writing operation in the selected memory blocks, each of said memory blocks comprising: a memory cell array including memory cells; a peripheral circuit operatively connected to said memory cell array, said peripheral circuit comprising: a holding current supplying circuit, operatively connected to said memory cell array, for supplying a holding current for holding data stored in said memory cells; bit lines operatively connected to said memory cells; a first current-source circuit, operatively connected to said bit lines, for supplying currents to said bit lines; a sense amplifier circuit, operatively connected to said bit lines, for detecting potential differences between said bit lines; and a second current-source circuit, operatively connected to said sense amplifier circuit, for supplying currents, other than those supplied by said first current-source circuit, to said sense amplifier circuit; and a holding-current controlling circuit, operatively connected to said peripheral circuit and said holding-current supplying circuit, for controlling said holding-current supplying circuit such that the holding-current supplied to an unselected-state memory block is greater than the holding-current supplied to a selected-state memory block, and such that the currents supplied from said first current-source circuit to said bit lines and the currents supplied from said second current-source circuit to said sense amplifier, assoicated with an unselected-state memory block, are smaller than the currents supplied from said first current-source circuit to said bit lines and the currents supplied from said second current-source circuit to said sense amplifier, associated with the selected-state memory block.
Claim 2
Dependent Claim
282 words
A static-type semiconductor memory device comprising: a plurality of memory blocks, arranged in rows and columns to form a matrix, having selected and unselected states, any one row of the memory blocks being selected to carry out a reading or writing operation in the selected memory blocks, each of said memory blocks comprising: a memory cell array including memory cells; a peripheral circuit operatively connected to said memory cell array, said peripheral circuit comprising: a holding current supplying circuit, operatively connected to said memory cell array, for supplying a holding current for holding data stored in said memory cells; bit lines operatively connected to said memory cells; a first current-source circuit, operatively connected to said bit lines, for supplying currents to said bit lines; a sense amplifier circuit, operatively connected to said bit lines, for detecting potential differences between said bit lines; and a second current-source circuit, operatively connected to said sense amplifier circuit, for supplying currents, other than those supplied by said first current-source circuit, to said sense amplifier circuit; and a holding-current controlling circuit, operatively connected to said peripheral circuit and said holding-current supplying circuit, for controlling said holding-current supplying circuit such that the holding-current supplied to an unselected-state memory block is greater than the holding-current supplied to a selected-state memory block, and such that the currents supplied from said first current-source circuit to said bit lines and the currents supplied from said second current-source circuit to said sense amplifier, assoicated with an unselected-state memory block, are smaller than the currents supplied from said first current-source circuit to said bit lines and the currents supplied from said second current-source circuit to said sense amplifier, associated with the selected-state memory block.
Claim 3
Dependent Claim
89 words
A static-type semiconductor memory device as set forth in claim 1, wherein said holding-current controlling circuit comprises a differential amplifier for determining whether the memory block is selected or not, said differential amplifier outputting a holding-current determining signal, said holding-current determining signal having a first potential when the memory block is selected and having a second potential when the memory block is unselected, said holding-currrent determining signal being supplied to said holding-current supplying circuit so as to activate said holding-current supplying circuit in response to only said first potential.
Claim 4
Dependent Claim
84 words
A static-type semiconductor memory device as set forth in claim 2, wherein said differential amplifier outputs a current-source current determining signal having said first potential when said holding-current determining signal has said second potential and having said second potential when said holding-current determining signal has said first potential, respectively, said current-source current determining signal being supplied to said first current-source and said second current-source, so as to activate said first and second current-source in response to the potential of said current-source current determining signal.
Claim 5
Dependent Claim
136 words
A static-type semiconductor memory device as set forth in claim 3, further comprising word lines and hold lines, wherein each of said memory cells is connected between one of said word lines and one of said hold lines, said word lines and hold lines extending in the row direction, said holding-current being conducted from each of said word lines through said memory cells to said hold lines, wherein each of said memory cells is operatively connected between a pair of bit lines extending in said column direction and wherein said holding-current supplying circuit comprises a plurality of first NPN transistors each having a base operatively connected to said differential amplifier, for receiving said holding-current determining signal, having a collector connected to one of said hold lines, and having an emitter connected to a first power supply.
Claim 6
Dependent Claim
38 words
A static-type semiconductor memory device as set forth in claim 4, wherein said first current-source circuit and said second current-source circuit comprise second NPN transistors each having a base operatively connected to receive said current-source current determining signal.
Claim 7
Dependent Claim
170 words
A static-type semiconductor memory device, operatively connected to receive a reference signal and a block selecting, as set forth in claim 5, wherein said differential amplifier comprises: a third NPN transistor having a base operatively connected to receive the reference signal, a collector operatively connected to a second power supply, and an emitter; a first resistor operatively connected between said second power supply and said collector of said third NPN transistor; a current-source operatively connected to said emitter of said third NPN transistor; a fourth NPN transistor having a base operatively connected to receive the block selecting signal, a collector operatively connected to said second power supply, and an emitter operatively connected to said current source; a second resistor operatively connected between said collector of said fourth NPN transistor and said second power supply; wherein said collector of said third NPN transistor provides said holding-current determining signal to said differential amplifier, and wherein said collector of said fourth NPN transistor provides said current-source current determining signal to said differential amplifier.
Claim 8
Dependent Claim
21 words
A static-type semiconductor memory device as set forth in claim 6, wherein each of said memory blocks is a memory chip.
Claim 9
Dependent Claim
23 words
A static-type semiconductor memory device as set forth in claim 6, wherein a predetermined number of said memory blocks comprise a memory chip.
Claim 10
Dependent Claim
237 words
A static-type semiconductor memory device comprising: a plurality of memory blocks, arranged in rows and columns to form a matrix, having selected and unselected states, said selected state memory blocks having a first holding-current and said unselected-state memory blocks having a second holding-current, any row of the memory blocks being selected to carry out a reading or writing operation in said selected-state memory blocks, each of said memory block comprising: a memory cell array including memory cells; a peripheral circuit operatively connected to said memory cell array, said peripheral circuit comprising: a holding-current supplying circuit, operatively connected to said memory cell array, for supplying the first and second holding-currents for holding data stored in said memory cells; bit lines operatively connected to said memory cells; a first current-source circuit, operatively connected to said bit lines, for supplying a first current to said bit lines of said selected memory cells; a sense amplifier circuit, operatively connected to said bit lines, for detecting potential differences between said bit lines; and a second current-source circuit, operatively connected to said sense amplifier circuit, for supplying the second current to said sense amplifier circuit of said unselected memory cells; and a holding-current controlling circuit, operatively connected to said peripheral circuit and said holding-current supplying circuit, for controlling said holding-current supplying circuit such that the second holding-current is greater than the first holding-current and the second current is less than the first current.
Claim 11
Dependent Claim
237 words
A static-type semiconductor memory device comprising: a plurality of memory blocks, arranged in rows and columns to form a matrix, having selected and unselected states, said selected state memory blocks having a first holding-current and said unselected-state memory blocks having a second holding-current, any row of the memory blocks being selected to carry out a reading or writing operation in said selected-state memory blocks, each of said memory block comprising: a memory cell array including memory cells; a peripheral circuit operatively connected to said memory cell array, said peripheral circuit comprising: a holding-current supplying circuit, operatively connected to said memory cell array, for supplying the first and second holding-currents for holding data stored in said memory cells; bit lines operatively connected to said memory cells; a first current-source circuit, operatively connected to said bit lines, for supplying a first current to said bit lines of said selected memory cells; a sense amplifier circuit, operatively connected to said bit lines, for detecting potential differences between said bit lines; and a second current-source circuit, operatively connected to said sense amplifier circuit, for supplying the second current to said sense amplifier circuit of said unselected memory cells; and a holding-current controlling circuit, operatively connected to said peripheral circuit and said holding-current supplying circuit, for controlling said holding-current supplying circuit such that the second holding-current is greater than the first holding-current and the second current is less than the first current.
Claim 12
Dependent Claim
165 words
A static-type semiconductor memory device, having a selected-state or unselected-state in accordance with a selection signal, comprising: a memory cell array including memory cells; holding-current supply means, operatively connected to said memory cell array, for supplying a holding-current to said memory cell array for holding data stored in said memory cells; peripheral circuit means, operatively connected to said memory cell array, for operating with said memory cell array during the selected-state; current-source circuit means, operatively connected to said peripheral current means, for supplying a peripheral current to said peripheral circuit means; and current control means, operatively connected to said holding-current supply means and said current-source circuit means, and operatively connected to receive the selection signal, for controlling said holding-current supply means and said current-source circuit means in accordance with the selection signal such that said holding-current during the unselected-state is greater than said holding-current during the selected-state, and such that said peripheral current during the unselected-state is smaller than said peripheral current during the selected-state.
Claim 13
Dependent Claim
165 words
A static-type semiconductor memory device, having a selected-state or unselected-state in accordance with a selection signal, comprising: a memory cell array including memory cells; holding-current supply means, operatively connected to said memory cell array, for supplying a holding-current to said memory cell array for holding data stored in said memory cells; peripheral circuit means, operatively connected to said memory cell array, for operating with said memory cell array during the selected-state; current-source circuit means, operatively connected to said peripheral current means, for supplying a peripheral current to said peripheral circuit means; and current control means, operatively connected to said holding-current supply means and said current-source circuit means, and operatively connected to receive the selection signal, for controlling said holding-current supply means and said current-source circuit means in accordance with the selection signal such that said holding-current during the unselected-state is greater than said holding-current during the selected-state, and such that said peripheral current during the unselected-state is smaller than said peripheral current during the selected-state.
Claim 14
Dependent Claim
95 words
A static-type semiconductor memory device as set forth in claim 10, wherein said current control means comprises a differential amplifier for determining whether said memory cell array is selected or unselected, said differential amplifier outputting a current control determining signal, said current control determining signal having a first potential when said memory cell array is selected and having a second potential when said memory cell array is unselected, said current control determining signal being supplied to said holding-current supply means so as to activate said holding-current supply means in response to only said first potential.
Claim 15
Dependent Claim
82 words
A static-type semiconductor memory device as set forth in claim 11, wherein said differential amplifier outputs a current-source current determining signal having said first potential when said current control determining signal has said second potential and having said second potential when said current control determining signal has said first potential, respectively, said current-source current determining signal being supplied to said current-source circuit means, so as to activate said current-source circuit means in response to the potential of said current-source current determining signal.
Claim 16
Dependent Claim
138 words
A static-type semiconductor memory device as set forth in claim 12, further comprising word lines and hold lines, wherein each of said memory cells is connected between one of said word lines and one of said hold lines, said word lines and said hold lines extending in the row direction, said holding-current being conducted from each of said word lines through said memory cells to said hold lines, wherein each of said memory cells is operatively connected between a pair of bit lines extending in said column direction, and wherein said current control means comprises a plurality of first NPN transistors each having a nase operatively connected to said differential amplifier, for receiving said current control determining signal, having a collector connected to one of said hold lines, and having an emitter connected to a first power supply.
Claim 17
Dependent Claim
33 words
A static-type semiconductor memory device as set forth in claim 13, wherein said current-source circuit means comprises a second NPN transistor having a base operatively connected to receive said current-source current determining signal.
Claim 18
Dependent Claim
176 words
A static-type semiconductor memory device, operatively connected to receive a reference signal and a block selecting signal, as set forth in claim 14, wherein said differential amplifier comprises: a third NPN transistor having a base operatively connected to receive the reference signal, having a collector operatively connected to a second power supply, and having an emitter; a first resistor operatively connected between said second power supply and said collector of said third NPN transistor; a current-source operatively connected to said emitter of said third NPN transistor; a fourth NPN transistor having a base operatively connected to receive the block selecting signal, having a collector operatively connected to said second power supply, and having an emitter operatively connected to said current-source; a second resistor operatively connected between said collector of said fourth NPN transistor and said second power supply; and wherein said collector of said third NPN transistor provides said current control determining signal to said differential amplifier, and wherein said collector of said fourth NPN transistor provides said current-source current determining signal to said differential amplifier.
Claim 19
Dependent Claim
21 words
A static-type semiconductor memory device as set forth in claim 15, wherein each of said memory blocks is a memory chip.
Claim 20
Dependent Claim
23 words
A static-type semiconductor memory device as set forth in claim 16, wherein a predetermined number of said memory blocks comprise a memory chip.
References Cited (Backward Citations)
US4369502A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-08-04 | 1990-02-03 | 1990-08-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-08-04 | 1994-02-03 | 1994-08-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-08-04 | 1998-02-03 | 1998-08-05 | $7700.00 | Window Closed / Lapsed |