Patent US6939789B2 successfully refreshed from Google Patents.
US4604728A
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US
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Semiconductor memory device
Assignee: FIJITSU Ltd A CORP OF JAPAN
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Filing: 1983-07-01
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Granted: 1986-08-05
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Expires: 2003-07-01
Abstract
Abstract A semiconductor memory device includes a plurality of static-type memory cells connected to pairs of word lines, each word line pair being composed of a word line having a high potential and a word line having a low potential, and a plurality of word-line discharging circuits, each being connected to one of the word line pairs. Each of the word-line discharging circuits includes, a thyristor whose anode is connected, via a voltage level shifter, to a word line having a high potential and whose cathode is connected to a constant-current source or a constant-voltage source. The thyristor comprises a PNP transistor and an NPN transistor. The NPN transistor can be a multi-emitter transistor or a multi-collector transistor whose second emitter or collector is connected to a word line having a low potential. If the NPN transistor is not a multi-emitter or multi-collector transistor, there is provided another NPN transistor whose base is connected to the base of the above-mentioned NPN transistor, whose collector is connected to the word line having a low potential, and whose emitter is connected to the second constant-current source or the second constant-voltage source.
Inventors
- 👤 Yoshinori Okajima
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 01:41
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/41; G11C11/413; G11C11/414; G11C11/415
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
130 words
A semiconductor memory device including pairs of word lines, and a first constant current source or a first constant voltage source, comprising: a plurality of static-type memory cells, respectively connected to the pairs of word lines, each of the pairs of word lines including a word line having a high potential and a word line having a low potential; and a plurality of word-line discharging circuits, each of said word line discharging circuits being connected to a respective one of the pairs of word lines, and comprising: a voltage level shifter operatively connected to the word lines having the high potential; and a thyristor having an anode operatively connected to said voltage level shifter and having a cathode operatively connected to the first constant-current source or the first constant-voltage source.
Claim 2
Dependent Claim
130 words
A semiconductor memory device including pairs of word lines, and a first constant current source or a first constant voltage source, comprising: a plurality of static-type memory cells, respectively connected to the pairs of word lines, each of the pairs of word lines including a word line having a high potential and a word line having a low potential; and a plurality of word-line discharging circuits, each of said word line discharging circuits being connected to a respective one of the pairs of word lines, and comprising: a voltage level shifter operatively connected to the word lines having the high potential; and a thyristor having an anode operatively connected to said voltage level shifter and having a cathode operatively connected to the first constant-current source or the first constant-voltage source.
Claim 3
Dependent Claim
73 words
A semiconductor memory device according to claim 1, wherein said thyristor comprises: a PNP transistor having a collector, having a base and having an emitter operatively connected to said voltage level shifter; and a first NPN transistor having a collector and having a base, respectively, operatively connected to the base and the collector of said PNP transistor, and having an emitter operatively connected to the first constant-current source or the first constant-voltage source.
Claim 4
Dependent Claim
51 words
A semiconductor memory device according to claim 2, wherein said first NPN transistor is a multi-emitter transistor, one of the emitters of said multi-emitter transistor being connected to the word lines having the low potential and another emitter thereof being connected to the first constant-current source or the first constant-voltage source.
Claim 5
Dependent Claim
47 words
A semiconductor memory device according to claim 2, wherein said first NPN transistor is a multi-collector transistor, one of the collectors of said multi-collector transistor being connected to the base of said PNP transistor and another collector being connected to the word lines having the low potential.
Claim 6
Dependent Claim
76 words
A semiconductor memory device according to claim 2, further comprising a second constant current source or a second constant voltage source and wherein each of said word-line discharging circuits comprises a second NPN transistor having a base operatively connected to the base of said first NPN transistor, having a collector operatively connected to the word lines having the low potential, and having an emitter operatively connected to the second constant-current source or the second constant-voltage source.
Claim 7
Dependent Claim
28 words
A semiconductor memory device according to claim 5, wherein the second constant-current source or the second constant-voltage source is provided commonly for all of the word-line discharging circuits.
Claim 8
Dependent Claim
28 words
A semiconductor memory device according to claim 5, wherein said word-line discharging circuit comprises a resistor operatively connected between the emitter and the collector of said PNP transistor.
Claim 9
Dependent Claim
28 words
A semiconductor memory device according to claim 2, wherein said word-line discharging circuit comprises a resistor operatively connected between the emitter and the collector of said PNP transistor.
Claim 10
Dependent Claim
25 words
A semiconductor memory device according to claim 1, wherein the constant-current source or constant-voltage source is provided commonly for all of the word-line discharging circuits.
Claim 11
Dependent Claim
31 words
A semiconductor memory device according to claim 1, wherein said voltage level shifter comprises a diode inserted between the word lines having the high potential and the anode of said thyristor.
Claim 12
Dependent Claim
31 words
A semiconductor memory device according to claim 1, wherein said voltage level shifter comprises a resistor inserted between the word lines having the high potential and the anode of said thyristor.
Claim 13
Dependent Claim
141 words
A word line discharging circuit operatively connected to a pair of word lines, one of the pair of word lines having a high potential and the other of the pair of word lines having a low potential, and operatively connectable to a first constant current source, comprising: a voltage level shifter operatively connected to the word line having the high potential; a PNP transistor having an emitter operatively connected to said voltage level shifter, having a base and having a collector; and a first NPN transistor having a base operatively connected to the collector of said PNP transistor, having a collector operatively connected to the base of said PNP transistor and having multi-emitters, one of the multi-emitters operatively connected to the first constant current source and another one of the multi-emitters operatively connected to the word line having the low potential.
Claim 14
Dependent Claim
141 words
A word line discharging circuit operatively connected to a pair of word lines, one of the pair of word lines having a high potential and the other of the pair of word lines having a low potential, and operatively connectable to a first constant current source, comprising: a voltage level shifter operatively connected to the word line having the high potential; a PNP transistor having an emitter operatively connected to said voltage level shifter, having a base and having a collector; and a first NPN transistor having a base operatively connected to the collector of said PNP transistor, having a collector operatively connected to the base of said PNP transistor and having multi-emitters, one of the multi-emitters operatively connected to the first constant current source and another one of the multi-emitters operatively connected to the word line having the low potential.
Claim 15
Dependent Claim
61 words
A word line discharging circuit according to claim 12, further comprising: a second NPN transistor having a base operatively connected to the base of said first NPN transistor, having a collector operatively connected to the word line having the low potential and having an emitter; and a second constant current source operatively connected to the emitter of said second NPN transistor.
Claim 16
Dependent Claim
25 words
A word line discharging circuit according to claim 13, further comprising a resistor operatively connected between the emitter and the collector of said PNP transistor.
Claim 17
Dependent Claim
142 words
A word line discharging circuit operatively connected to a pair of word lines, one of the pair of word lines having a high potential and the other one of the pair of word lines having a low potential, and operatively connectable to a first constant current source, comprising: a voltage level shifter operatively connected to the word line having the high potential; a PNP transistor having an emitter operatively connected to said voltage level shifter, having a base and having a collector; and a first NPN transistor having a base operatively connected to the collector of said PNP transistor, having an emitter operatively connected to the first constant current source, and having multi-collectors, one of the multi-collectors operatively connected to the word line having the low potential and another one of the multi-collectors operatively connected to the base of said PNP transistor.
Claim 18
Dependent Claim
142 words
A word line discharging circuit operatively connected to a pair of word lines, one of the pair of word lines having a high potential and the other one of the pair of word lines having a low potential, and operatively connectable to a first constant current source, comprising: a voltage level shifter operatively connected to the word line having the high potential; a PNP transistor having an emitter operatively connected to said voltage level shifter, having a base and having a collector; and a first NPN transistor having a base operatively connected to the collector of said PNP transistor, having an emitter operatively connected to the first constant current source, and having multi-collectors, one of the multi-collectors operatively connected to the word line having the low potential and another one of the multi-collectors operatively connected to the base of said PNP transistor.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-08-04 | 1990-02-03 | 1990-08-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-08-04 | 1994-02-03 | 1994-08-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-08-04 | 1998-02-03 | 1998-08-05 | $7700.00 | Window Closed / Lapsed |