US4604684A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Digital computer having unique instruction decoding logic
Assignee: PMC Inc
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Filing: 1983-11-15
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Granted: 1986-08-05
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Expires: 2003-11-15
Abstract
Abstract Method and apparatus for improving instruction decoding in a microcode-controlled digital computer system. The microinstruction sequences are made simple and compact enough that sufficient complexity is required in the instruction decoding logic that it is feasible to custom-configure a gate array to perform instruction decoding. The resultant gate array, by virtue of being embodied in a single integrated circuit, is extremely fast and compact and has low power requirements.
Inventors
- 👤 David I. Epstein
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 10:22
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/22; G06F9/26; G06F9/261
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
66 words
A method of increasing speed of instruction decoding in a microcode-controlled digital computer, comprising the steps of: employing a gate array comprising on a single chip and in a single encapsulation the gating necessary to decode the operation code of an instruction; and, producing from said gate array the control store address of a sequence of microinstructions that will effect the operation specified by said instruction.
Claim 2
Independent Claim
66 words
A method of increasing speed of instruction decoding in a microcode-controlled digital computer, comprising the steps of: employing a gate array comprising on a single chip and in a single encapsulation the gating necessary to decode the operation code of an instruction; and, producing from said gate array the control store address of a sequence of microinstructions that will effect the operation specified by said instruction.
Claim 3
Dependent Claim
114 words
In an improved digital computer system having a main memory for storing instructions and data and a CPU responsive to said instructions for processing said data, said CPU including microcode control means which includes a control store containing a sequence of microinstructions corresponding to each one of said instructions for controlling operation of said CPU, the improvement comprising: said microcode control means including instruction decoding means embodied in a gate array consisting of a single integrated circuit for obtaining from each instruction the control store address of said sequence of microinstructions corresponding to each of said instructions, whereby said control store address is rapidly obtained thereby facilitating operational speed of said digital computer system.
Claim 4
Dependent Claim
114 words
In an improved digital computer system having a main memory for storing instructions and data and a CPU responsive to said instructions for processing said data, said CPU including microcode control means which includes a control store containing a sequence of microinstructions corresponding to each one of said instructions for controlling operation of said CPU, the improvement comprising: said microcode control means including instruction decoding means embodied in a gate array consisting of a single integrated circuit for obtaining from each instruction the control store address of said sequence of microinstructions corresponding to each of said instructions, whereby said control store address is rapidly obtained thereby facilitating operational speed of said digital computer system.
Claim 5
Dependent Claim
42 words
In the digital computer system of claim 2, said microcode control means including other means for obtaining from said each instruction said cntrol store address of said sequence of microinstructions corresponding to each of said instructions in no more than thirty-five nanoseconds.
Claim 6
Dependent Claim
132 words
In an improved digital computer system having a main memory for storing instructions and data and a CPU responsive to said instructions for processing said data, said CPU including microcode control means which includes a control store containing a sequence of microinstructions corresponding to each one of said instructions for controlling operation of said CPU, the improvement comprising: said microcode control means including instruction decoding means embodied in a gate array consisting of a single integrated circuit for obtaining from each instruction the control store address of said sequence of microinstructions corresponding to each of said instructions, said microcode control means further including other means for obtaining from said each instruction said control store address of said sequence of microinstructions corresponding to each of said instructions in no more than thirty-five nanoseconds.
Claim 7
Dependent Claim
132 words
In an improved digital computer system having a main memory for storing instructions and data and a CPU responsive to said instructions for processing said data, said CPU including microcode control means which includes a control store containing a sequence of microinstructions corresponding to each one of said instructions for controlling operation of said CPU, the improvement comprising: said microcode control means including instruction decoding means embodied in a gate array consisting of a single integrated circuit for obtaining from each instruction the control store address of said sequence of microinstructions corresponding to each of said instructions, said microcode control means further including other means for obtaining from said each instruction said control store address of said sequence of microinstructions corresponding to each of said instructions in no more than thirty-five nanoseconds.
Claim 8
Independent Claim
276 words
A method of increasing the speed of instruction decoding in a microcode-controlled digital computer, decoding being the generation of a control store address of a sequence of microinstructions corresponding to the instruction, each instruction comprising no more than a first number of bits, each instruction being a member of one class of instructions of a plurality of classes of instructions, the method comprising the steps of: (a) determining the class of which an instruction to be decoded is a member; (b) producing a first group of one or more specifier bits in response to the determination of the instruction's class, each class producing a unique first group; (c) producing a second group of specifier bits, the number of bits in the second group being a second number, the second number being less than a third number by the number of bits in the first group, the third number being less than the first number, the second group of specifier bits being produced from a second number of the bits in the instruction (i) selecting, in response to the determination of the instruction's class, a second number of the bit positions of the instruction; (ii) providing, in response to the determination of the instruction's class, first certain of the selected instructions bits as bits in the second group of specifier bits; and (iii) providing complements of the remaining selected instruction bits as bits in the second group of specifier bits; and (d) concatenating the first group of specifier bits and the second group of specifier bits to produce the control store address, the number of bits in the control store address being equal to the third number.
Claim 9
Independent Claim
276 words
A method of increasing the speed of instruction decoding in a microcode-controlled digital computer, decoding being the generation of a control store address of a sequence of microinstructions corresponding to the instruction, each instruction comprising no more than a first number of bits, each instruction being a member of one class of instructions of a plurality of classes of instructions, the method comprising the steps of: (a) determining the class of which an instruction to be decoded is a member; (b) producing a first group of one or more specifier bits in response to the determination of the instruction's class, each class producing a unique first group; (c) producing a second group of specifier bits, the number of bits in the second group being a second number, the second number being less than a third number by the number of bits in the first group, the third number being less than the first number, the second group of specifier bits being produced from a second number of the bits in the instruction (i) selecting, in response to the determination of the instruction's class, a second number of the bit positions of the instruction; (ii) providing, in response to the determination of the instruction's class, first certain of the selected instructions bits as bits in the second group of specifier bits; and (iii) providing complements of the remaining selected instruction bits as bits in the second group of specifier bits; and (d) concatenating the first group of specifier bits and the second group of specifier bits to produce the control store address, the number of bits in the control store address being equal to the third number.
Claim 10
Dependent Claim
11 words
The method of claim 5 wherein the first number is sixteen.
Claim 11
Dependent Claim
11 words
The methof of claim 5 wherein the third number is nine.
References Cited (Backward Citations)
US4354228A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-08-04 | 1990-02-03 | 1990-08-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-08-04 | 1994-02-03 | 1994-08-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-08-04 | 1998-02-03 | 1998-08-05 | $7700.00 | Window Closed / Lapsed |