Method and circuit for correcting a record timing

Claim 2

A record timing correction method in a magnetic recording apparatus for writing on a record medium digital data consisting of a plurality of bits translated to include i to i+k "0" bits between adjacent "1" bits, comprising the steps of: detecting the state of a bit at a specified position in the digital data serially recorded on said record medium and the state of the i-th bit from said specified position; designating a normal timing in the data recording when the state of the bit at said specified position is "1" and the number "if" of "0" bits between the "1" bit at said specified position and a preceding "1" bit is equal to i+k and the number "ir" of "0" bits between the "1" bit at said specified position and a next "1" bit is equal to i+k, designating an early timing in the data recording when the number "if"=i and the number "ir">i, and designating a late timing in the data recording when the number "if"≧i and the number "ir"=i or when the number "if"≧i+1 and the number "ir"=i+1; and correcting the record timing to provide said normal timing, said early timing or said late timing, whereby the output data is produced at said normal timing, said early timing or said late timing depending on the bit pattern designation.

Claim 3

A record timing correction method according to claim 1, wherein the number i of the "0" bits between the adjacent "1" bits in said data is more than one.

Claim 4

A record timing correction method according to claim 1, wherein the number i of the "0" bits between the adjacent "1" bits in said data is two and the number i+k is no more than seven.

Claim 5

A record timing correction method according to claim 3, wherein said designating step discriminates an intermediate timing later than said normal timing and earlier than said late timing when the number "if"≧3 and the number "ir"=3, and said record timing correction step produces the output data at said intermediate timing when said intermediate timing is designated.

Claim 6

A record timing correction method according to claim 2, wherein the number i of the "0" bits between the adjacent "1" bits in the data is one and the number i+k is no more than eight.

Claim 7

A record timing correction circuit in a magnetic recording apparatus for writing on a record medium digital data consisting of a plurality of bits translated to include i to i+k "0" bits between adjacent "1" bits, comprising: bit extraction means for extracting a bit at a specified position in said digital data and the i-th bit from said specified position; pattern discrimination means connected to receive the extracted bits from said bit extraction means for designating a normal timing for data recording when the state of the bit at said specified position is "1" and the number "if" of "0" bits between the "1" bit at said specified position and a preceding "1" bit is equal to i+k and the number "ir" of "0" bits between the "1" bit at said specified position and a next "1" bit is equal to i+k, designating an early timing for data recording when the number "if"=i and the number "ir">i and designating a late timing for the data recording when the number "if"≧i and the number "ir"=i or when the number "if"≧i+1 and the number "ir"=i+1; and record timing correction means for writing the digital data at the normal timing, the early timing or the late timing in accordance with the bit pattern designation provided by said pattern discrimination means.

Claim 8

A record timing correction circuit in a magnetic recording apparatus for writing on a record medium digital data consisting of a plurality of bits translated to include i to i+k "0" bits between adjacent "1" bits, comprising: bit extraction means for extracting a bit at a specified position in said digital data and the i-th bit from said specified position; pattern discrimination means connected to receive the extracted bits from said bit extraction means for designating a normal timing for data recording when the state of the bit at said specified position is "1" and the number "if" of "0" bits between the "1" bit at said specified position and a preceding "1" bit is equal to i+k and the number "ir" of "0" bits between the "1" bit at said specified position and a next "1" bit is equal to i+k, designating an early timing for data recording when the number "if"=i and the number "ir">i and designating a late timing for the data recording when the number "if"≧i and the number "ir"=i or when the number "if"≧i+1 and the number "ir"=i+1; and record timing correction means for writing the digital data at the normal timing, the early timing or the late timing in accordance with the bit pattern designation provided by said pattern discrimination means.

Claim 9

A record timing correction circuit according to claim 6, wherein the number i of the "0" bits between the adjacent "1" bits in said data is more than one.

Claim 10

A record timing correction circuit according to claim 6, wherein the number if of the "0" bits between the adjacent "1" bits in said data is two and the number i+k is no more than seven.

Claim 11

A record timing correction circuit according to claim 8, wherein said pattern discrimination means designates an intermediate timing later than said normal timing and earlier than said late timing when the number "if"≧3 and the number "ir"=3, and said record timing correction means produces the output data at said intermediate timing when said intermediate timing is designated.

Claim 12

A record timing correction circuit according to claim 6, wherein the number i of the "0" bits between the adjacent "1" bits in the data is one and the number i+k is no more than eight.

Claim 13

A record timing correction circuit according to claim 6, wherein said bit extraction means is a shift register having a plurality of series-connected flip-flops for serially shifting input bits, the bit outputs of a center flip-flop and at least two flip-flops spaced by i forward and behind said center flip-flop being extracted, said pattern discrimination means including a plurality of AND circuits for ANDing the output of said center flip-flop and the outputs of said at least two flip-flops to discriminate said normal timing, said early timing or said late timing, and said record timing correction means including a plurality of delay circuits for sequentially delaying an external clock and a plurality of flip-flops connected to receive the discrimination result from said pattern discrimination means for producing the output data at the timing of the external clock or the delayed clock in accordance with the discrimination result.

Claim 14

A record timing correction circuit according to claim 9, wherein said bit extraction means is a shift register having a plurality of series-connected flip-flops for serially shifting input bits, the bit outputs of a center flip-flop and at least two flip-flops spaced by i forward and behind said center flip-flop being extracted, said pattern discrimination means including a plurality of AND circuits for ANDing the output of said center flip-flop and the outputs of said at least two flip-flops to discriminate said normal timing, said early timing or said late timing, and said record timing correction means including a plurality of delay circuits for sequentially delaying an external clock and a plurality of flip-flops connected to receive the discrimination result from said pattern discrimination means for producing the output data at the timing of the external clock or the delayed clock in accordance with the discrimination result.

Claim 15

A record timing correction circuit according to claim 10, wherein said bit extraction means is a shift register having a plurality of series-connected flip-flops for serially shifting input bits, the bit outputs of a center flip-flop and at least two flip-flops spaced by i forward and behind said center flip-flop being extracted, said pattern discrimination means including a plurality of AND circuits for ANDing the output of said center flip-flop and the outputs of said at least two flip-flops to discriminate said normal timing, said early timing or said late timing, and said record timing correction means including a plurality of delay circuits for sequentially delaying an external clock and a plurality of flip-flops connected to receive the discrimination result from said pattern discrimination means for producing the output data at the timing of the external clock or the delayed clock in accordance with the discrimination result.