US4603397A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Binary coded decimal number division apparatus
Assignee: Hitachi Ltd
•
Filing: 1983-01-31
•
Granted: 1986-07-29
•
Expires: 2003-01-31
Abstract
Abstract In preparation of addresses of a quotient prediction table used in a binary coded decimal number division scheme with predetermined bits of a dividend and a divisor in binary coded decimal representation, the addresses are modified with the redundant bits. The absolute bit number for the addresses is thus decreased, whereby data quantity and hence capacity of RAM required for implementing the quotient prediction table can be significantly reduced, while satisfactory function of the quotient prediction table being assured. The apparatus for the binary coded decimal number division is implemented inexpensively in a small size.
Inventors
- 👤 Toru Ohtsuki
- 👤 Yoshio Oshima
- 👤 Sako Ishikawa
- 👤 Masaharu Fukuta
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 12:54
CPC Classifications
G; G06; G06F; G06F7/00; G06F7/38; G06F7/48; G06F7/491; G06F7/4915; G06F7/4917
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
278 words
An apparatus for division of binary coded decimal numbers in which a quotient is determined on a digit-by-digit basis from a dividend and a divisor represented in binary coded decimal notation, respectively, by referring to a quotient prediction table which furnishes a digit value corresponding to the correct quotient or value greater than it by one, the value furnished by said quotient prediction table being subtracted by one when said value does not correspond to the correct quotient, comprising: a dividend-remainder register; a divisor register; a memory for storing the quotient prediction table having a reduced data capacity for compressed address bit length: a quotient register connected to the output of said memory; an address decoder coupled to receive divisor bits and dividend bits from said divisor register and said dividend register, respectively, for decoding said received bits to generate addresses of said quotient prediction table; and means responsive to a digit value read out of said memory as provided in said quotient register and the contents of said dividend-register and said divisor register for generating a quotient; said address decoder including address bit length determining means for determining, in accordance with the most significant digit value of the divisor, the numbers of significant bits of said dividend and said divisor necessary for deriving the predicted quotient; and address modification means responsive to said address length determining means for modifying the necessary number of significant bits thus determined so as to be rearranged into an address bit series of a reduced bit length as an address output based on bit-compressive decode logic predetermined essentially using redundant bits in binary coded decimal representation of said divisor and said dividend.
Claim 2
Independent Claim
278 words
An apparatus for division of binary coded decimal numbers in which a quotient is determined on a digit-by-digit basis from a dividend and a divisor represented in binary coded decimal notation, respectively, by referring to a quotient prediction table which furnishes a digit value corresponding to the correct quotient or value greater than it by one, the value furnished by said quotient prediction table being subtracted by one when said value does not correspond to the correct quotient, comprising: a dividend-remainder register; a divisor register; a memory for storing the quotient prediction table having a reduced data capacity for compressed address bit length: a quotient register connected to the output of said memory; an address decoder coupled to receive divisor bits and dividend bits from said divisor register and said dividend register, respectively, for decoding said received bits to generate addresses of said quotient prediction table; and means responsive to a digit value read out of said memory as provided in said quotient register and the contents of said dividend-register and said divisor register for generating a quotient; said address decoder including address bit length determining means for determining, in accordance with the most significant digit value of the divisor, the numbers of significant bits of said dividend and said divisor necessary for deriving the predicted quotient; and address modification means responsive to said address length determining means for modifying the necessary number of significant bits thus determined so as to be rearranged into an address bit series of a reduced bit length as an address output based on bit-compressive decode logic predetermined essentially using redundant bits in binary coded decimal representation of said divisor and said dividend.
Claim 3
Independent Claim
285 words
An apparatus for division of binary coded decimal numbers in which a quotient is determined on a digit-by-digit basis from a dividend and a divisor represented in binary coded decimal notation, respectively, by referring to a quotient prediction table which furnishes a digit value corresponding to the correct quotient or value greater than it by one, the value furnished by said quotient prediction table being substracted by one when said value does not correspond to the correct quotient, comprising: a dividend-remainder register; a divisor register; a memory for storing the quotient prediction table having a reduced data capacity for compressed address bit length; a quotient register connected to the output of said memory; an address decoder coupled to receive divisor bits and dividend bits from said divisor register and said dividend register, respectively, for decoding said received bits to generate addresses of said quotient prediction table; and means responsive to a digit value read out of said memory as provided in said quotient register and the contents of said dividend-remainder register and said divisor register for generating a quotient; said address decoder including address bit length determining means for determining, in accordance with the most significant digit value of the divisor, the numbers of significant bits of said dividend and said divisor necessary for deriving the predicted quotient; and address modification means responsive to said address bit length determining means for modifying the necessary number of significant bits thus determined to allot them in an address bit series of a reduced bit length based on a bit-compressing decode format predetermined essentially using redundant bits (1010) 2 -(1111) 2 in binary coded decimal reoresentation of said dividend and said divisor to thereby provide an address output.
Claim 4
Independent Claim
285 words
An apparatus for division of binary coded decimal numbers in which a quotient is determined on a digit-by-digit basis from a dividend and a divisor represented in binary coded decimal notation, respectively, by referring to a quotient prediction table which furnishes a digit value corresponding to the correct quotient or value greater than it by one, the value furnished by said quotient prediction table being substracted by one when said value does not correspond to the correct quotient, comprising: a dividend-remainder register; a divisor register; a memory for storing the quotient prediction table having a reduced data capacity for compressed address bit length; a quotient register connected to the output of said memory; an address decoder coupled to receive divisor bits and dividend bits from said divisor register and said dividend register, respectively, for decoding said received bits to generate addresses of said quotient prediction table; and means responsive to a digit value read out of said memory as provided in said quotient register and the contents of said dividend-remainder register and said divisor register for generating a quotient; said address decoder including address bit length determining means for determining, in accordance with the most significant digit value of the divisor, the numbers of significant bits of said dividend and said divisor necessary for deriving the predicted quotient; and address modification means responsive to said address bit length determining means for modifying the necessary number of significant bits thus determined to allot them in an address bit series of a reduced bit length based on a bit-compressing decode format predetermined essentially using redundant bits (1010) 2 -(1111) 2 in binary coded decimal reoresentation of said dividend and said divisor to thereby provide an address output.
Claim 5
Dependent Claim
61 words
A binary coded decimal number division apparatus according to claim 2, wherein the bit numbers of said dividend and said divisor in binary coded decimal representation which are required for obtaining the predicted quotient include 11 significant bits and 8 significant bits, respectively, and the address bit series of a reduced bit number for said quotient prediction table contains 12 bits.
Claim 6
Dependent Claim
267 words
A binary coded decimal number division apparatus according to claim 3, wherein when the bit series of said divisor is represented by x 0 x 1 x 2 x 3 x 4 x 5 x 6 x 7 the bit series of said dividend is represented by y 0 y 1 y 2 y 3 y 4 y 5 y 6 y 7 y 8 y 9 y 10 and said address bit series is represented by a 0 a 1 a 2 a 3 a 4 a 5 a 6 a 7 a 8 a 9 a 10 a ll , decoded outputs are produced in accordance with the following logical expressions: a 0 =x 0 ·x 1 ·x 2 +x 1 ·x 2 ·x 6 +x 1 ·x 2 ·x 3 ·x 6 a 1 =x 0 ·x 1 ·x 2 ·y 8 +x 1 ·x 2 ·x 6 +x 1 a 2 =x 0 ·x 1 ·x 2 9 ·y 9 +x 2 a 3 =x 0 ·x 1 ·x 2 ·y 10 +x 1 ·x 2 ·x 3 ·x 6 +(x 0 +x 1 +x 2 )·x 3 a 4 =x 4 +y 4 a 5 =x 5 +y 4 a 6 =x 0 ·x 1 ·x 7 +(x 0 +x 1 )·y 1 a 7 =x 0 ·x 1 ·x 2 ·x 6 +(x 0 +x 1 +x 2 )·y 2 a 8 =y 3 a 9 =y 5 +x 4 ·y 4 a 10 =y 6 +x 5 ·y 4 a 11 =x 0 ·y 7 +x 0 ·y 0 .
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-07-28 | 1990-01-27 | 1990-07-29 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-07-28 | 1994-01-27 | 1994-07-29 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-07-28 | 1998-01-27 | 1998-07-29 | $7700.00 | Window Closed / Lapsed |