US4602225A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Apparatus for frequency correction in a frequency synthesizer
Assignee: Agilent Technologies Inc
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Filing: 1984-06-24
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Granted: 1986-07-22
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Expires: 2004-06-24
Abstract
Abstract The present invention provides apparatus and a method for determining and correcting frequency offset for use in a frequency synthesizer to provide external control and DC frequency modulation of the synthesizer output frequency. The technique provides DCFM capability by unlocking a phase-lock loop (PLL) which provides the synthesizer reference frequency and making the PLL oscillator (VCO) tune line available for external inputs. Utilizing a frequency counting circuit, the exact output frequency of the VCO is determined. The desired VCO frequency is compared with the actual VCO frequency to derive an error signal proportional to any offset in the VCO frequency resulting from unlocking the PLL. The error signal is then utilized to compensate (the synthesizer output signal) for any frequency change as a result of unlocking the PLL.
Inventors
- 👤 Brian M. Miller
- 👤 Charles R. Kogler
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 20:23
CPC Classifications
H; H03; H03C; H03C3/00; H03C3/02; H03C3/09; H03C3/0908; H03C3/095
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
308 words
A closed loop frequency synthesizer for generating a final output signal, said synthesizer comprising: frequency generating means responsive to an input signal and a reference signal, said frequency generating means for generating the final output signal; a first phase-locked loop coupled to the frequency generating means, said first phase-locked loop having a tunable oscillator, said tunable oscillator responsive to a tune voltage on a tune line to adjust the frequency of the tunable oscillator, said first phase-locked loop for synthesizing a first signal having a predetermined frequency when the phase-locked loop is locked, said first signal comprising said reference signal when the first phase-locked loop is locked; voltage source means for biasing said tunable oscillator; switching means for unlocking said first phase-locked loop, coupling the tunable oscillator to said voltage source and for making the tune line available for inputting DC frequency modulation signals, said tunable oscillator responsive to said voltage source to generate a second signal having a frequency close to said predetermined frequency, said second signal comprising the reference signal when said first phase-locked loop is unlocked; control means coupled to the first phase-locked loop, said control means including frequency counter means, said frequency counter means for counting the frequency of said second signal, said control means responsive to said second signal and a third signal, said third signal indicative of said predetermined frequency, said control means providing an error signal indicative of the frequency difference between said second signal and said third signal; and a second phase-locked loop coupled to said frequency generating means and to said control means, said second phase-locked loop for providing said input-signal, said second phase-locked loop responsive to said error signal to compensate said input signal to correct the final output signal for the effect of the frequency difference in the reference signal when said first phase-locked loop is unlocked.
Claim 2
Dependent Claim
308 words
A closed loop frequency synthesizer for generating a final output signal, said synthesizer comprising: frequency generating means responsive to an input signal and a reference signal, said frequency generating means for generating the final output signal; a first phase-locked loop coupled to the frequency generating means, said first phase-locked loop having a tunable oscillator, said tunable oscillator responsive to a tune voltage on a tune line to adjust the frequency of the tunable oscillator, said first phase-locked loop for synthesizing a first signal having a predetermined frequency when the phase-locked loop is locked, said first signal comprising said reference signal when the first phase-locked loop is locked; voltage source means for biasing said tunable oscillator; switching means for unlocking said first phase-locked loop, coupling the tunable oscillator to said voltage source and for making the tune line available for inputting DC frequency modulation signals, said tunable oscillator responsive to said voltage source to generate a second signal having a frequency close to said predetermined frequency, said second signal comprising the reference signal when said first phase-locked loop is unlocked; control means coupled to the first phase-locked loop, said control means including frequency counter means, said frequency counter means for counting the frequency of said second signal, said control means responsive to said second signal and a third signal, said third signal indicative of said predetermined frequency, said control means providing an error signal indicative of the frequency difference between said second signal and said third signal; and a second phase-locked loop coupled to said frequency generating means and to said control means, said second phase-locked loop for providing said input-signal, said second phase-locked loop responsive to said error signal to compensate said input signal to correct the final output signal for the effect of the frequency difference in the reference signal when said first phase-locked loop is unlocked.
Claim 3
Independent Claim
184 words
A method for DC frequency modulation of an output signal generated by a frequency synthesizer comprising a plurality of phase-locked loops and an internal frequency counter, said method comprising: synthesizing a predetermined frequency within a first phase-locked loop, said first phase-locked loop comprising a tunable oscillator responsive to a tune voltage on a tune line, to provide a reference signal; unlocking said first phase-locked loop to make the tunable oscillator tune line available for DC frequency modulation input signals for modulating said reference signal; biasing said tunable oscillator to a fixed tune voltage source for tuning said tunable oscillator to a first frequency close to said predetermined frequency; counting said first frequency and providing a first signal indicative of said first frequency; comparing said first signal with a second signal, said second signal indicative of said predetermined frequency, for providing an error signal indicative of the difference between said predetermined frequency and said first frequency; and utilizing said error signal in a second phase-locked loop responsive to said error signal to compensate the output signal for said difference in frequency of said reference frequency.
Claim 4
Independent Claim
184 words
A method for DC frequency modulation of an output signal generated by a frequency synthesizer comprising a plurality of phase-locked loops and an internal frequency counter, said method comprising: synthesizing a predetermined frequency within a first phase-locked loop, said first phase-locked loop comprising a tunable oscillator responsive to a tune voltage on a tune line, to provide a reference signal; unlocking said first phase-locked loop to make the tunable oscillator tune line available for DC frequency modulation input signals for modulating said reference signal; biasing said tunable oscillator to a fixed tune voltage source for tuning said tunable oscillator to a first frequency close to said predetermined frequency; counting said first frequency and providing a first signal indicative of said first frequency; comparing said first signal with a second signal, said second signal indicative of said predetermined frequency, for providing an error signal indicative of the difference between said predetermined frequency and said first frequency; and utilizing said error signal in a second phase-locked loop responsive to said error signal to compensate the output signal for said difference in frequency of said reference frequency.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-07-21 | 1990-01-20 | 1990-07-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-07-21 | 1994-01-20 | 1994-07-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-07-21 | 1998-01-20 | 1998-07-22 | $7700.00 | Window Closed / Lapsed |