US4602168A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Low offset CMOS comparator circuit
Assignee: National Semiconductor Corp
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Filing: 1984-03-28
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Granted: 1986-07-22
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Expires: 2004-03-28
Abstract
Abstract A CMOS comparator circuit is disclosed in which a low offset is achieved without trimming. The input stage is composed of a pair of bipolar transistors which have lateral non-dedicated collectors that operate in parallel with the substrate dedicated collectors. The input stage includes matched load devices and is followed by an amplifier having a differential to single ended converter.
Inventors
- 👤 Peter S. Single
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 19:09
CPC Classifications
H; H03; H03K; H03K5/00; H03K5/22; H03K5/24; H03K5/2436; H03K5/2445
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
111 words
A CMOS comparator circuit having a single ended output terminal and first and second differential input terminals, said circuit comprising: an input stage comprising a pair of bipolar transistors, each one having an emitter, a base, a substrate dedicated collector, and a lateral collector adjacent to said emitter; means for coupling said input stage transistor bases to said comparator input terminals; means for coupling said pair of bipolar transistor emitters together and to a constant current sink to provide differential operation; matched transistor load means coupled to said lateral collectors of said pair of bipolar transistors; and amplifier means for coupling said matched transistor load means to said comparator output terminal.
Claim 2
Dependent Claim
111 words
A CMOS comparator circuit having a single ended output terminal and first and second differential input terminals, said circuit comprising: an input stage comprising a pair of bipolar transistors, each one having an emitter, a base, a substrate dedicated collector, and a lateral collector adjacent to said emitter; means for coupling said input stage transistor bases to said comparator input terminals; means for coupling said pair of bipolar transistor emitters together and to a constant current sink to provide differential operation; matched transistor load means coupled to said lateral collectors of said pair of bipolar transistors; and amplifier means for coupling said matched transistor load means to said comparator output terminal.
Claim 3
Dependent Claim
18 words
The comparator circuit of claim 1 wherein said amplifier means includes a differential to single ended converter circuit.
Claim 4
Dependent Claim
29 words
The comparator circuit of claim 2 wherein said amplifier means further includes an amplifier stage having a cascode load coupled to drive said differential to single ended converter circuit.
Claim 5
Dependent Claim
32 words
The comparator circuit of claim 3 wherein said differential to single ended converter includes a P-channel transistor inverter and an N-channel transistor inverter and said N-channel transistor inverter includes time delay means.
References Cited (Backward Citations)
US4429234A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-07-21 | 1990-01-20 | 1990-07-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-07-21 | 1994-01-20 | 1994-07-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-07-21 | 1998-01-20 | 1998-07-22 | $7700.00 | Window Closed / Lapsed |