Monitoring circuit for an electronic postage meter

Claim 2

A monitoring circuit for an electronic postage meter operating under control of a programmed microprocessor, including: a transistor switch for receiving an output signal from the programmed microprocessor and generating an output signal in response thereto; timer means electrically coupled to said transistor switch for generating an output pulse in the absence of a signal from said transistor switch within a predetermined time interval; logic gate means electrically coupled to said timer means for holding its output in a first logical state in the absence of a signal from said timer means and capable of changing its output to a seacond logical state in the presence of an output signal from said timer means; said logic gate means includes an OR gate and a NAND gate, said OR gate having one input connected to said timer means and its output connected to the input of said NAND gate, the output of said NAND gate being connected to the microprocessor; and means coupled as another input to said OR gate for holding the output of said NAND gate in a desired logical state during testing.

Claim 3

The monitoring circuit recited in claim 1, wherein: said timer means includes a comparator which is capable of being reset by an input signal.

Claim 4

The monitoring circuit recited in claim 1, wherein: said transistor switch means includes a capacitor for maintaining a d.c. bias.

Claim 5

The monitoring circuit recited in claim 1, wherein: said timer means resets itself if a signal is received from said input means in approximately 10 milliseconds.

Claim 6

The monitoring circuit recited in claim 1, including: means coupled to said timer means to disable the monitoring circuit during power up of the microprocessor.

Claim 7

A monitoring circuit for an electronic postage meter operating under control of a programmed microprocessor, including: a transistor electrically coupled to the microprocessor, said transistor providing an output signal in response to an input from the microprocessor; a comparator electrically coupled to the output of said transistor for providing an output signal in the absence of receiving a signal from said transistor within a predetermined time interval; logic means coupled to the output of said comparator, said logic means including an OR gate having one input coupled to the output of said comparator and a NAND gate having one input coupled to the output of said OR gate, said NAND gate having its output held in a first logical state in the absence of a signal from said comparator, the output of said NAND gate chaning to a second logical state in the presence of an output signal from said comparator, said NAND gate having its output electrically connected to the programmed microprocessor to advise the same of a change in the logical state of its output; and means coupled to said logic gate means for holding the same in a desired logical state during testing.

Claim 8

A monitoring circuit for an electronic postage meter operating under control of a programmed microprocessor, including: a transistor electrically coupled to the microprocessor, said transistor providing an output signal in response to an input from the microprocessor; a comparator electrically coupled to the output of said transistor for providing an output signal in the absence of receiving a signal from said transistor within a predetermined time interval; logic means coupled to the output of said comparator, said logic means including an OR gate having one input coupled to the output of said comparator and a NAND gate having one input coupled to the output of said OR gate, said NAND gate having its output held in a first logical state in the absence of a signal from said comparator, the output of said NAND gate chaning to a second logical state in the presence of an output signal from said comparator, said NAND gate having its output electrically connected to the programmed microprocessor to advise the same of a change in the logical state of its output; and means coupled to said logic gate means for holding the same in a desired logical state during testing.

Claim 9

The monitoring circuit recited in claim 6, wherein: said comparator provides an output pulse to said OR gate to change the logical state of the output of said NAND gate if a signal is not received from said transistor within an interval of approximately 10 milliseconds.

Claim 10

The monitoring circuit recited in claim 6, including: a timing capacitor coupled to said comparator.

Claim 11

The monitoring circuit recited in claim 6, including: a diode for disabling the monitoring circuit during power up of the microprocessor.