US4599631A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor apparatus having a zener diode integral with a resistor-transistor combination
Assignee: Toshiba Corp
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Filing: 1983-10-05
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Granted: 1986-07-08
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Expires: 2003-10-05
Abstract
Abstract A semiconductor apparatus includes a p + -type region formed in the surface area of an n - -type semiconductor layer formed on a p-type semiconductor substrate, and an n + -type region which is formed in a contact relationship with respect to the p + -type region and forms a Zener diode in conjunction with the p + -type region. A p-type region is further formed in the surface area of the semiconductor layer and is electrically connected to the n + -type region by a contact layer. The n + -type region forms a resistor between the contact layer and the p + -type region. The p-type region, semiconductor layer and substrate constitute a pnp transistor.
Inventors
- 👤 Mitsuo Tsuzuki
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 09:31
CPC Classifications
H; H10; H10D; H10D8/00; H10D8/20; H10D8/25; H10D84/00; H10D84/60; H10D84/611; H10D84/613
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
161 words
A semiconductor apparatus comprising: a semiconductor substrate of one conductivity type; a semiconductor layer of an opposite conductivity type formed on said semiconductor substrate; a first and a second semiconductor region of said one conductivity type separately formed in the surface area of said semiconductor layer, apart from each other; a third semiconductor region of the opposite conductivity type which is formed in the surface area of said semiconductor layer and has a higher impurity concentration than said semiconductor layer, said third semiconductor region being formed in a contact relationship with respect to said first semiconductor region, a Zener diode being formed in the junction between said first and third semiconductor regions; and connecting means for electrically connecting said second and third semiconductor regions; wherein said second semiconductor region, semiconductor layer and semiconductor substrate constitute a transistor; and wherein that portion of said third semiconductor region which lies between said connecting means and said first semiconductor region acts as a resistor.
Claim 2
Dependent Claim
161 words
A semiconductor apparatus comprising: a semiconductor substrate of one conductivity type; a semiconductor layer of an opposite conductivity type formed on said semiconductor substrate; a first and a second semiconductor region of said one conductivity type separately formed in the surface area of said semiconductor layer, apart from each other; a third semiconductor region of the opposite conductivity type which is formed in the surface area of said semiconductor layer and has a higher impurity concentration than said semiconductor layer, said third semiconductor region being formed in a contact relationship with respect to said first semiconductor region, a Zener diode being formed in the junction between said first and third semiconductor regions; and connecting means for electrically connecting said second and third semiconductor regions; wherein said second semiconductor region, semiconductor layer and semiconductor substrate constitute a transistor; and wherein that portion of said third semiconductor region which lies between said connecting means and said first semiconductor region acts as a resistor.
Claim 3
Dependent Claim
42 words
A semiconductor apparatus according to claim 1, wherein said second and third semiconductor regions are formed in contact with each other, and wherein said connecting means has a conductive layer formed on the junction area between said second and third semiconductor regions.
Claim 4
Dependent Claim
21 words
A semiconductor apparatus according to claim 2, wherein said one conductivity type is p-type and said opposite conductivity type is n-type.
Claim 5
Dependent Claim
51 words
A semiconductor apparatus according to claim 2, further comprising a buried layer of the opposite conductivity type, which is formed in the boundary area between said semiconductor substrate and said semiconductor layer, in the location corresponding to said first semiconductor region, and has a higher impurity concentration than the semiconductor layer.
Claim 6
Dependent Claim
36 words
A semiconductor apparatus according to claim 2, further comprising a fourth semiconductor region of said one conductivity type which is formed to surround said semiconductor layer and has a higher impurity concentration than said semiconductor substrate.
Claim 7
Dependent Claim
47 words
A semiconductor apparatus according to claim 5, further comprising a fifth semiconductor region of said one conductivity type which is formed in the surface area of said semiconductor layer in contact with said fourth semiconductor region and an opposing relationship with respect to said second semiconductor region.
Claim 8
Dependent Claim
51 words
A semiconductor apparatus according to claim 1, further comprising a buried layer of the opposite conductivity type which is formed in the boundary area between said semiconductor substrate and said semiconductor layer, in the location corresponding to said first semiconductor region and has a higher impurity concentration than the semiconductor layer.
Claim 9
Dependent Claim
36 words
A semiconductor apparatus according to claim 1, further comprising a fourth semiconductor region of said one conductivity type which is formed to surround said semiconductor layer and has a higher impurity concentration than said semiconductor substrate.
Claim 10
Dependent Claim
45 words
A semiconductor apparatus according to claim 8, further comprising a fifth semiconductor region of said one conductivity type formed in the surface area of said semiconductor layer in contact with said fourth semiconductor region and an opposing relationship with respect to said second semiconductor region.
References Cited (Backward Citations)
DE2028632A1
Cited
US4080616A
Cited
US4100561A
Cited
US4258311A
Cited
US4267557A
Cited
JPS5571075A
Cited
US4451839A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-07-07 | 1990-01-06 | 1990-07-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-07-07 | 1994-01-06 | 1994-07-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-07-07 | 1998-01-06 | 1998-07-08 | $7700.00 | Window Closed / Lapsed |