Secure microprocessor

Claim 2

A program security device, having an external and an internal data bus, comprising: conditional bidirectional inverter means for combining input data with a variable, said inverter means having a variable input bus, a ciphered data select, an input enable, an output enable, a first and a second input/output bus, said ciphered data select being coupled to receive a ciphered text data signal, said input enable being coupled to receive an input enabling signal, said output enable being coupled to receive an output enable signal, said first input/output bus being coupled to said external bus of said program security device; bidirectional permutor means for rearranging data bus lines, said permutor means having a reset, a first program bus, a second program bus, a first and a second input/output bus, said reset being coupled to receive a reset signal, said first input/output bus being coupled to said second input/output bus of said inverter means and said second input/output bus being coupled to said internal data bus of said program security device; and bidirectional bypass means for bypassing said inverter means and said permutor means, said bypass means having a plain text data select, a first and a second input/output bus, said plain text data select being coupled to receive a plain text data signal, said first input/output bus being coupled to said external data bus of said program security device and said second input/output bus being coupled to said internal data select of said program security device.

Claim 3

The program security device of claim 1 wherein said conditional bidirectional inverter means comprises: a first control gate having a first input, a second input and an output, said first input being coupled to said ciphered data select and said second input being coupled to said input enable; a second control gate having a first input, a second input and an output, said first input being coupled to said ciphered data select and said second input being coupled to said output enable; a first set of logic gates each having an input, an output and an enable, said enables being coupled to said output of said first control gate and said outputs being coupled to said second input/output bus of said conditional bidirecional inverter means; a second set of logic gates each having a first input, a second input, and an output, said first inputs being coupled to said first input/output bus of said conditional bidirectional inverter means, said second inputs being coupled to said variable input bus of said conditional bidirectional inverter means and said outputs being coupled to said inputs of said first set of logic gates; a third set of logic gates each having an input, an output and an enable, said enables being coupled to said output of said second control gate and said output being coupled to said first input/output bus of said conditional bidirectional inverter means; and a fourth set of logic gates each having a first input, a second input and an output, said first inputs being coupled to said second input/output data bus of said conditional bidirectional inverter means, said second inputs being coupled to said variable input bus of said conditional bidirectional inverter means and said outputs being coupled to said inputs of said third set of logic gates.

Claim 4

The program security device of claim 2 wherein said bidirectional permutor means comprises a first array having a reset, a first data bus, a second data bus, a third data bus and a fourth data bus, said reset being coupled to said reset of said bidirectional permutor means, said first data bus being coupled to said first input/output bus of said bidirectional permutor means, said second data bus being coupled to said second input/output bus of said bidirectional permutor means, said third data bus being coupled to said first program bus of said bidirectional permutor means and said fourth data bus being coupled to said second program bus of said bidirectional permutor means.

Claim 5

The program security device of claim 3 wherein said first array comprises a plurality of fifth logic gates each having a reset, a first input/output, a second input/output, a first program line and a second program line, said reset line being coupled to said reset of said first array, said first input/output lines being coupled to said first data bus of said first array, said second input/output lines being coupled to said second data bus of said first array, said first program lines being coupled to said third data bus of said first array and said second program lines being coupled to said fourth data bus of said first array.

Claim 6

The program security device of claim 4 wherein said bidirectional bypass means comprises a plurality of sixth logic gates each having an enable, a first input/output line and a second input/output line, said enables being coupled to said plain text data select, said first input/output lines being coupled to said first input/output bus of said bidirectional bypass means and said second input/output lines being coupled to said second input/output bus of said bidirectional bypass means.

Claim 7

The program security device of claim 5 further comprising a programming circuit having a reset, a strobe line, a cipher line, a first data bus, a second data bus, a third data bus, a fourth data bus and a fifth data bus, said reset being coupled to receive a reset signal, said strobe line being coupled to receive a strobe signal, said cipher line being coupled to receive a cipher signal, said first data bus being coupled to receive data from a processor, said second data bus being coupled to receive data from said processor, said third data bus being coupled to said first program bus of said bidirectional permutor means, said fourth data bus being coupled to said second program bus of said bidirectional permutor means and said fifth data bus being coupled to said variable input bus of said conditional bidirectional inverter means.

Claim 8

The program security device of claim 6 wherein said programming circuit means comprises: a first register having a first data bus and a second data bus, said first data bus being coupled to said first data bus of said programming circuit means; a seventh set of logic gates each having a first input, a second input and an output, said first inputs being coupled to said second data bus of said first register, said second inputs being coupled to said strobe input of said programming circuit means and said outputs being coupled to said third data bus of said programming circuit means; a storage device having a cipher input, a first data bus, a second data bus and a third data bus, said cipher input being coupled to said cipher line and said first data bus being coupled to said second data bus of said first register; an eighth set of logic gates each having a first input, a second input and an output, said first inputs being coupled to said third data bus of said storage device; a decoder having an input data bus and an output data bus, said input data bus being coupled to the outputs of said eighth set of logic gates and said output data bus being coupled to said fourth data bus of said programming circuit means; a second register having a first data bus, a second data bus and a third data bus, said first data bus being coupled to said second data bus of said programming circuit, said second data bus being coupled to said second inputs of said eighth set of logic gates and said third data bus being coupled to said second data bus of said storage device; a ninth set of logic gates each having a first input, a second input and an output, said first inputs being coupled to said third data bus of said second register and said second inputs being coupled to said strobe line of said programming circuit means; and a second array having a reset, a first data bus, a second data bus and a third data bus, said reset being coupled to said reset of said programming circuit means, said first data bus being coupled to said outputs of said eighth set of logic gates, said second data bus being coupled to said outputs of said ninth set of logic gates and said third data bus being coupled to said second data bus of said programming circuit means.

Claim 9

The program security device of claim 7 wherein said first control gate, said second control gate, said seventh set of logic gates and said ninth set of logic gates are comprised of dual input AND gates.

Claim 10

The program security device of claim 8 wherein said second set of logic gates, said fourth set of logic gates and said eighth set of logic gates are comprised of dual input exclusive OR gates.

Claim 11

The program security device of claim 9 wherein said first set of logic gates, said third set of logic gates and said plurality of sixth logic gates are comprised of bidirectional transmission gates.

Claim 12

A program security device, having an external and an internal data bus, comprising: bidirectional bypass means for coupling said external and internal data buses, said bidirectional bypass means having a plain text data select, a first data bus and a second data bus, said plain text data select being coupled to receive a plain text data signal, said first data bus being coupled to said external data bus of said program security device and said second data bus being coupled to said internal data bus of said internal program security device; conditional bidirectional inverter means for combining input data with a variable, said conditional bidirectional inverter having an output enable, an input enable, a cipher text data select, a first data bus, a second data bus and a variable input bus, said output enable being coupled to receive an output enabling signal, said input enable being coupled to receive an input enabling signal, said ciphered text data select being coupled to receive a ciphered text data signal and said first data bus being coupled to said external data bus of said program security device; bidirectional permutor means for rearranging data bus lines, said permutor having a reset, a first data bus, a second data bus, a first program bus and a second program bus, said reset being coupled to receive a reset signal, said first data bus being coupled to said internal data bus of said program security device and said second data bus being coupled to said third data bus of said conditional bidirectional inverter means; a seventh set of logic gates each having a first input, a second input and an output, said first inputs being coupled to a strobe line for receiving a strobe signal and said outputs being coupled to said fourth data bus of said permutor means; a first register means having a first data bus and a second data bus, said first data bus being coupled to said second inputs of said seventh set of logic gates and said second data bus being coupled to a processor; a storage device having a first data bus, a second data bus and a third data bus, said first data bus being coupled to said first data bus of said first register; an eighth set of logic gates each having a first input, a second input and an output, said second inputs being coupled to said second data bus of said storage device; a second register having a first data bus, a second data bus and a third data bus, said first data bus being coupled to said processor, said second data bus being coupled to said third data bus of said storage device and said third data bus being coupled to said first inputs of said eighth set of logic gates; a decoder having a first data bus and a second data bus, said first data bus being coupled to said outputs of said eighth set of logic gates and said second data bus being coupled to said third data bus of said permutor means; a ninth set of logic gates each having a first input, a second input and an output, said first inputs being coupled to said second data bus of said second register and said second inputs being coupled to said strobe line; and a second array having a first data bus, a second data bus, a third data bus and a reset, said reset being coupled to receive said reset signal, said first data bus being coupled to said second data bus of said decoder, said second data bus being coupled to said outputs of said ninth set of logic gates and said third data bus being coupled to said second data bus of said conditional bidirectional inverter means.

Claim 13

A program security device, having an external and an internal data bus, comprising: bidirectional bypass means for coupling said external and internal data buses, said bidirectional bypass means having a plain text data select, a first data bus and a second data bus, said plain text data select being coupled to receive a plain text data signal, said first data bus being coupled to said external data bus of said program security device and said second data bus being coupled to said internal data bus of said internal program security device; conditional bidirectional inverter means for combining input data with a variable, said conditional bidirectional inverter having an output enable, an input enable, a cipher text data select, a first data bus, a second data bus and a variable input bus, said output enable being coupled to receive an output enabling signal, said input enable being coupled to receive an input enabling signal, said ciphered text data select being coupled to receive a ciphered text data signal and said first data bus being coupled to said external data bus of said program security device; bidirectional permutor means for rearranging data bus lines, said permutor having a reset, a first data bus, a second data bus, a first program bus and a second program bus, said reset being coupled to receive a reset signal, said first data bus being coupled to said internal data bus of said program security device and said second data bus being coupled to said third data bus of said conditional bidirectional inverter means; a seventh set of logic gates each having a first input, a second input and an output, said first inputs being coupled to a strobe line for receiving a strobe signal and said outputs being coupled to said fourth data bus of said permutor means; a first register means having a first data bus and a second data bus, said first data bus being coupled to said second inputs of said seventh set of logic gates and said second data bus being coupled to a processor; a storage device having a first data bus, a second data bus and a third data bus, said first data bus being coupled to said first data bus of said first register; an eighth set of logic gates each having a first input, a second input and an output, said second inputs being coupled to said second data bus of said storage device; a second register having a first data bus, a second data bus and a third data bus, said first data bus being coupled to said processor, said second data bus being coupled to said third data bus of said storage device and said third data bus being coupled to said first inputs of said eighth set of logic gates; a decoder having a first data bus and a second data bus, said first data bus being coupled to said outputs of said eighth set of logic gates and said second data bus being coupled to said third data bus of said permutor means; a ninth set of logic gates each having a first input, a second input and an output, said first inputs being coupled to said second data bus of said second register and said second inputs being coupled to said strobe line; and a second array having a first data bus, a second data bus, a third data bus and a reset, said reset being coupled to receive said reset signal, said first data bus being coupled to said second data bus of said decoder, said second data bus being coupled to said outputs of said ninth set of logic gates and said third data bus being coupled to said second data bus of said conditional bidirectional inverter means.

Claim 14

The program security device of claim 11 wherein said conditional bidirectional inverter means comprises: a first control gate having a first input, a second input and an output, said first input being coupled to said ciphered data select and said second input being coupled to said input enable; a second control gate having a first input, a second input and an output, said first input being coupled to said ciphered data select and said second input being coupled to said output enable; a first set of logic gates each having an input, an output and an enable, said enables being coupled to said output of said first control gate and said outputs being coupled to said second input/output bus of said conditional bidirectional inverter means; a second set of logic gates each having a first input, a second input, and an output, said first inputs being coupled to said external data bus of said conditional bidirectional inverter means, said second inputs being coupled to said variable input bus of said conditional bidirectional inverter means and said outputs being coupled to said inputs of said first set of logic gates; a third set of logic gates each having an input, an output and an enable, said enables being coupled to said output of said second control gate and said outputs being coupled to said external data bus of said program security device; and a fourth set of logic gates each having a first input, a second input and an output, said first inputs being coupled to said second input/output data bus of said conditional bidirectional inverter means, said second inputs being coupled to said variable input bus of said conditional bidirectional inverter means and said outputs being coupled to said inputs of said third set of logic gates.

Claim 15

The security device of claim 12 wherein said bidirectional permutor means comprises a first array having a reset, a first data bus, a second data bus, a third data bus and a fourth data bus, said reset being coupled to receive a reset signal, said first data bus being coupled to said first data bus of said bidirectional permutor means, said second data bus being coupled to said second data bus of said bidirectional permutor means, said third data bus being coupled to said first program bus of said bidirectional permutor means and said fourth data bus being coupled to said second program bus of said bidirectional permutor means.

Claim 16

The program security device of claim 13 wherein said first array comprises a plurality of fifth logic gates each having a reset, a first input/output, a second input/output, a first program line and a second program line, said first reset lines being coupled to said reset of said first array, said first input/output lines being coupled to said first data bus of said first array, said second input/output lines being coupled to said second data bus of said first array, said first program lines being coupled to said first program bus of said first array and said second program lines being coupled to said second program bus of said first array.

Claim 17

The program security device of claim 14 wherein said bidirectional bypass means comprises a plurality of fixed logic gates each having an enable, a first input/output line and a second input/output line, said enables being coupled to said plain text data select, said first input/output lines being coupled to said external data bus of said program security device and said second input/output lines being coupled to said internal data bus of said program security device.

Claim 18

The program security device of claim 15 wherein said first control gate, said second control gate, said seventh set of logic gates and said ninth set of logic gates are comprised of dual input AND gates.

Claim 19

The progam security device of claim 16 wherein said second set of logic gates, said fourth set of logic gates and said eighth set of logic gates are comprised of dual input exclusive OR gates.

Claim 20

The program security device of claim 17 wherein said first set of logic gates, said third set of logic gates and said plurality of sixth logic gates are comprised of bidirectional transmission gates.