US4596984A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Digital data input circuit
Assignee: Mitsubishi Electric Corp
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Filing: 1983-09-16
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Granted: 1986-06-24
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Expires: 2003-09-16
Abstract
Abstract In a digital data input circuit, a number of switches arranged in matrix of m rows by n columns (m, n: integer being equal to one or more) are operated in ON/OFF state and signals are obtained to represent setting state of the switches, amplifying means which are additionally connected before and after the switches are driven directly by power including ripple voltage generated by rectifying AC power, and pulse train signal for strobing output signal of the amplifier is generated from the power including the ripple voltage.
Inventors
- 👤 Noritaka Egami
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 16:20
CPC Classifications
H; H03; H03M; H03M11/00; H03M11/22; G; G06; G06F; G06F17/00; H03K; H03K17/00; H03K17/002; H03K17/51; H03K17/56; H03K17/60; H03K17/62; H03K17/6221; H03K17/78; H03K17/795; H03K17/7955
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
141 words
Digital data input circuit, wherein a number of switches arranged in matrix of m rows by an columns (m, n: integer being equal to one or more) are operated in ON/Off state, signals are supplied sequentially through first amplifying means to the corresponding switches of each of said n columns during phase periods different from each other, said signals being taken out of the switches of m rows through second amplifying means; said input circuit comprising rectifying means for rectifying AC power in full-wave rectification and supplying the rectified power as an output voltage to the first and second amplifying means, and signal generating means for converting the waveform of said output voltage of the rectifying means and generating a pulse train in synchronization with the frequency of the AC power source for enabling output signals of the second amplifying means.
Claim 2
Dependent Claim
141 words
Digital data input circuit, wherein a number of switches arranged in matrix of m rows by an columns (m, n: integer being equal to one or more) are operated in ON/Off state, signals are supplied sequentially through first amplifying means to the corresponding switches of each of said n columns during phase periods different from each other, said signals being taken out of the switches of m rows through second amplifying means; said input circuit comprising rectifying means for rectifying AC power in full-wave rectification and supplying the rectified power as an output voltage to the first and second amplifying means, and signal generating means for converting the waveform of said output voltage of the rectifying means and generating a pulse train in synchronization with the frequency of the AC power source for enabling output signals of the second amplifying means.
Claim 3
Dependent Claim
26 words
Digital data input circuit as set forth in claim 1, characterized in that said rectifying means is a full-wave rectifier composed of diodes in bridge connection.
Claim 4
Dependent Claim
49 words
Digital data input circuit as set forth in claim 1, characterized in that said signal generating means comprises a photocoupler including a light-emitting diode for receiving output voltage of the rectifying means and a phototransistor connected optically with the light-emitting diode for generating the pulse train from collector thereof.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-06-23 | 1989-12-23 | 1990-06-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-06-23 | 1993-12-23 | 1994-06-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-06-23 | 1997-12-23 | 1998-06-24 | $7700.00 | Window Closed / Lapsed |