Digital phase-locked loop

Claim 2

A digital phase-locked loop for receiving an input data signal having a predetermined bit frequency, comprising: (a) means for producing a clock signal having a frequency nominally equal to the bit frequency of the input data signal, (b) means responsive to the clock signal for producing a control signal containing three control pulses in each clock period, thereby dividing each clock period into three regions corresponding to early, normal and late arrival of the data signal relative to the clock signal, (c) means responsive to the control signal for deciding which region the data signal occurs in, and for advancing the clock signal by 90° in phase if the data signal occurs in the early region and retarding the clock signal by 90° in phase if the data signal occurs in the late region, and (d) means for outputting said clock signal coupled to said means for deciding.

Claim 3

A digital phase-locked loop for receiving an input data signal having a predetermined bit frequency, comprising: (a) oscillator means for producing a first clock signal having a frequency nominally equal to n times the bit frequency of the input data, (b) counter means responsive to the first clock signal, for dividing the frequency of the first clock signal by n to produce a second clock signal having a frequency nominally equal to the bit frequency of the input data, (c) means responsive to the second clock signal for producing a control signal containing three control pulses in each period of the second clock signal, thereby dividing each period of the second clock signal into three regions corresponding to early, normal and late arrival of the data signal relative to the second clock signal, (d) means responsive to the input data signal and to a first occurrence of any one of said three control pulses following the input data signal, for producing a resetting pulse of predetermined duration delayed by a predetermined amount with respect to any one of said three control pulses, (e) means for applying the resetting pulse to the counter means to reset the counter means, thereby advancing the second clock signal by 90° in phase if the data signal occurs in the early region and retarding the second clock signal by 90° in phase if the data signal occurs in the late region, and (f) means for outputting said second clock signal coupled to said means for applying.

Claim 4

A digital phase-locked loop for receiving an input data signal having a predetermined bit frequency, comprising: (a) oscillator means for producing a first clock signal having a frequency nominally equal to n times the bit frequency of the input data, (b) counter means responsive to the first clock signal, for dividing the frequency of the first clock signal by n to produce a second clock signal having a frequency nominally equal to the bit frequency of the input data, (c) means responsive to the second clock signal for producing a control signal containing three control pulses in each period of the second clock signal, thereby dividing each period of the second clock signal into three regions corresponding to early, normal and late arrival of the data signal relative to the second clock signal, (d) means responsive to the input data signal and to a first occurrence of any one of said three control pulses following the input data signal, for producing a resetting pulse of predetermined duration delayed by a predetermined amount with respect to any one of said three control pulses, (e) means for applying the resetting pulse to the counter means to reset the counter means, thereby advancing the second clock signal by 90° in phase if the data signal occurs in the early region and retarding the second clock signal by 90° in phase if the data signal occurs in the late region, and (f) means for outputting said second clock signal coupled to said means for applying.

Claim 5

A phase-locked loop according to claim 2 wherein the counter comprises first and second bistables each having a clock input, a data input, a normal output and an inverted output, the bistables being so connected that the normal output of the first bistable is connected to the data input of the second bistable and the inverted output of the second bistable is connected to the data input of the first bistable whereby the counter has a cycle of four states, and the clock inputs of both bistables being connected to receive said first clock signal.

Claim 6

A phase-locked loop according to claim 3, wherein the means for producing the control pulses comprises gating means for producing a control pulse when the first bistable is set and the second bistable unset, or when the second bistable is set and the first clock signal which drives the counter is at a low logic level.