US4596003A
Expired / Lapsed
US
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Semiconductor memory
Assignee: Mitsubishi Electric Corp
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Filing: 1984-02-15
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Granted: 1986-06-17
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Expires: 2004-02-15
Abstract
Abstract A semiconductor memory which comprises a memory section including a plurality of memory cell groups, each group including a plurality of memory cells; each of said memory cell groups including a circuitry arrangement in which the memory cells in each column are connected by a bit line, and in which the memory cells in each row are connected by a first word line; each of said first word lines having a second word line mating therewith, said second word line being made of aluminum; each of said memory cell groups including a column decoder for selecting one from said bit lines and a row decoder for selecting one from said second word lines each in accordance with an input address signal; and a group selecting unit including a group selecting decoder and a group selecting circuit, whereby said first and second word lines are connected or disconnected so as to enable the memory operation to be conducted group by group.
Inventors
- 👤 Hiroshi Shimizu
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 11:24
CPC Classifications
G; G11; G11C; G11C8/00; G11C8/14; G11C8/12
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
217 words
A semiconductor memory comprising: l pieces of memory cell groups each of which has a matrix of memory cells arrayed in m rows and n j columns (j=1 . . . l; l is an integer more than or equal to 2); a plurality of bit lines each of which is connected to all said memory cells in each column in each of said memory cell groups; a column decoder for selecting a particular bit line from said bit lines in accordance with an input address signal; (m×l) first word lines each of which is connected to all said memory cells in each row in each of said memory cell groups; m pieces of second word lines of aluminum provided for each of the m rows in common through all of said memory cell groups; a row decoder for selecting a particular word line from said m second word lines in accordance with an input address signal; (m×l) group selecting circuits provided between said paired first and second word lines, whereby said first and second word lines are connected and disconnected; a group selecting decoder for selecting one from said memory cell groups so as to effect m group selecting circuits for the selected memory cell group including a memory cell corresponding to the input address signal.
Claim 2
Dependent Claim
217 words
A semiconductor memory comprising: l pieces of memory cell groups each of which has a matrix of memory cells arrayed in m rows and n j columns (j=1 . . . l; l is an integer more than or equal to 2); a plurality of bit lines each of which is connected to all said memory cells in each column in each of said memory cell groups; a column decoder for selecting a particular bit line from said bit lines in accordance with an input address signal; (m×l) first word lines each of which is connected to all said memory cells in each row in each of said memory cell groups; m pieces of second word lines of aluminum provided for each of the m rows in common through all of said memory cell groups; a row decoder for selecting a particular word line from said m second word lines in accordance with an input address signal; (m×l) group selecting circuits provided between said paired first and second word lines, whereby said first and second word lines are connected and disconnected; a group selecting decoder for selecting one from said memory cell groups so as to effect m group selecting circuits for the selected memory cell group including a memory cell corresponding to the input address signal.
Claim 3
Dependent Claim
32 words
A semiconductor memory as defined in claim 1, wherein said bit lines are integrated with an upper aluminum layer, and wherein said second word lines are integrated with a lower aluminum layer.
Claim 4
Dependent Claim
18 words
A semiconductor memory as defined in claim 2, wherein said first word line is made of polysilicon layer.
Claim 5
Dependent Claim
34 words
A semiconductor memory as defined in claim 1, further comprising a plurality of sense circuits for each of said memory cell groups, whereby an output is drawn from each of said memory cell groups.
Claim 6
Dependent Claim
69 words
A semiconductor memory as defined in claim 1, wherein said group selecting circuit is constructed with two field-effect transistors (FET) serially connected to said second word line and the ground, and wherein said first word line is connected to the connecting node of said two FETs, and a true level and a compliment level from said group selecting decoder are respectively applied to the gates of said two FETs.
Claim 7
Dependent Claim
171 words
A semiconductor memory as defined in claim 1, wherein said memory cell comprises a first FET connected between a first potential line and a first node and having its gate connected to a second node, a second FET connected between said first node and a second potential line and having its gate connected to said second node, a third FET connected between said first potential line and said second node and having its gate connected to said first node, a fourth FET connected between said second node and said second potential line and having its gate connected to said first node, a fifth FET connected between one of paired said bit lines and said first node and having its gate connected to said first word line, and a sixth FET connected between the other of said paired bit lines and said second node and having its gate connected to said first word line, thereby allowing complimentary signals of said true and compliment levels to appear at said first and second nodes.
Claim 8
Dependent Claim
143 words
A semiconductor memory as defined in claim 6, wherein said second potential line and one terminals of said second and fourth FETs are connected to each other through a ground line integrated with a lower aluminum layer, said ground line being arranged in the first, second, and third leg of four legs surrounding said first to sixth FETs, said second word line being integrated with said lower aluminum layer insulated from said ground line, and having a part thereof arranged at a position corresponding to the fourth leg of said four legs inside said first word line connected to the gates of said fifth and sixth FETs, said paired bit lines being integrated with an upper aluminum layer formed on said lower aluminum layer, and being located in parallel with as well as inside said ground lines along said first and second leg.
Claim 9
Dependent Claim
18 words
A semiconductor memory as defined in claim 7, wherein said first word lines are made of polysilicon layer.
References Cited (Backward Citations)
US4542485A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-06-16 | 1989-12-16 | 1990-06-17 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-06-16 | 1993-12-16 | 1994-06-17 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-06-16 | 1997-12-16 | 1998-06-17 | $7700.00 | Window Closed / Lapsed |