Method for control of automatic mechanical transmission system utilizing a microprocessor based electronic controller

Claim 1

An improved method of controlling a vehicle automatic mechanical transmission system comprising a throttling device controlled engine, and operator actuated throttle position indication device, a multi-speed jaw clutch type change gear transmission, a nonpositive coupling device drivingly interposed the engine and the transmission and actuators responsive to command signals for controlling the status of said throttling device, coupling device and transmission, said method including utilizing a digital microprocessor based electronic control unit for processing current and stored inputs in accordance with predetermined logic routines to determine desired engaged ratio of the transmission and to generate command outputs to said actuators, said control unit having means to receive inputs indicative of at least transmission input shaft speed, transmission output shaft speed, engine speed and operator actuated throttle position and means to condition and store said input information; said improved method comprising the steps of: selecting a critical control period based upon the rates of response of said throttling device, coupling device and transmission actuators and the frequency of adjusting said actuators required to assure the speed of said vehicle engine will not vary during said critical control period by greater than a predetermined nominal value; arranging said predetermined logic routines into a first alogorithm routine and a second algorithm routine, said microprocessor in said first algorithm routine processing current inputs to provide a processed output signal indicative of the desired engaged ratio of the transmission, said microprocessor in said second algorithm routine processing said then current input signals, including said processed output signal, to generate output signals, including command output signals to said actuators, independently of previously processed input and generated output signals; providing performance logic rules for said microprocessor wherein said microprocessor performs said first algorithm routine on a continuous loop basis and is responsive to a periodic signal to interrupt performance of said first algorithm routine to completely perform said second algorithm and then to resume performance of said first algorithm routine from the point of interruption; generating said periodic signal at a frequency sufficient to cause at least two interruptions of said first algorithm and complete executions of said second algorithm during said critical control period.