US4594656A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Memory refresh apparatus
Assignee: Individual
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Filing: 1985-12-17
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Granted: 1986-06-10
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Expires: 2005-12-17
Abstract
Abstract A memory refresh control scheme is provided wherein the refresh timing and address signals are independent of memory configuration or the configuration of an interface unit. Since the system relates to a distributed memory arrangement, the refresh control signal and the refresh address signals are simultaneously sent to the corresponding address portions of each of the concerned memory sections and to the interface units. The logic involved in generating the refresh signal includes a first counter, driven by the system clock, which periodically generates the refresh request control signal. A second counter generates a digital address for the portion of the memory units to be refreshed. The second counter is incremented by each successive output control signal from the first counter. The digital address generated by the second counter along with the control signal generated by the first counter are simultaneously transmitted to each memory sector and to the interface unit directly associated with those memory sectors. In a distributed system there will be more than one interface unit with its associated memory sectors. Since a feature of the distributed system is the intercommunication between the component parts, it is necessary that the refresh request signal and the refresh address signals be synchronized with respect to the other units.
Inventors
- 👤 Richard C. Moffett
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 15:21
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/14; G06F13/16; G06F13/1605; G06F13/161; G06F13/1636; G11; G11C; G11C11/00; G11C11/46
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
375 words
A distributed digital data processing system comprising: a first computer subsystem including a first control processing unit (CPU), a first central interface unit (CIU), and a first volatile random access memory unit (MU); and a second computer subsystem including a second central processing unit (CPU), a second central interface unit (CIU) and a second volatile random access memory unit (MU), each MU storing digital data signals, being divided into m sections, with each section being divided into n groups, where m and n are integers greater than one and including means for refreshing the data signals stored there. first means providing communications between the first CIU and the first and second CPU's, and between the first CIU and the first and second MU's, second means providing communications between the second CIU and the first and second CPU's, and between the second CIU and the first and second MU's, all communications between a CPU and an MU being controlled by and transmitted through a CIU; a system control center including a first clock subsystem for the first computer subsystem and a second clock subsystem for the second computer subsystem, each clock system providing timing signals, refresh request signals and refresh address signals, the refresh address signals specifying a memory group, third circuit means for applying the refresh request and refresh address signals of the first clock subsystem to the first CIU and first MU, fourth circuit means for applying the refresh request and refresh address signals of the second clock subsystem to the second CIU and the second MU, the first CIU in response to the receipt of a refresh request signal producing a refresh strobe ($REF) which is applied to the first MU and which causes the means for refreshing data signals to refresh data signals stored in the addressed blocks of the first MU; the second CIU in response to the receipt of a refresh request signal producing a refresh strobe ($REF) which is applied to the second MU and which causes the means for refreshing the data signals to refresh the data signals stored in the addressed blocks of the second MU; and means for synchronizing the issuance of the refresh request and refresh address signals by the first and second clock subsystems.
Claim 2
Dependent Claim
375 words
A distributed digital data processing system comprising: a first computer subsystem including a first control processing unit (CPU), a first central interface unit (CIU), and a first volatile random access memory unit (MU); and a second computer subsystem including a second central processing unit (CPU), a second central interface unit (CIU) and a second volatile random access memory unit (MU), each MU storing digital data signals, being divided into m sections, with each section being divided into n groups, where m and n are integers greater than one and including means for refreshing the data signals stored there. first means providing communications between the first CIU and the first and second CPU's, and between the first CIU and the first and second MU's, second means providing communications between the second CIU and the first and second CPU's, and between the second CIU and the first and second MU's, all communications between a CPU and an MU being controlled by and transmitted through a CIU; a system control center including a first clock subsystem for the first computer subsystem and a second clock subsystem for the second computer subsystem, each clock system providing timing signals, refresh request signals and refresh address signals, the refresh address signals specifying a memory group, third circuit means for applying the refresh request and refresh address signals of the first clock subsystem to the first CIU and first MU, fourth circuit means for applying the refresh request and refresh address signals of the second clock subsystem to the second CIU and the second MU, the first CIU in response to the receipt of a refresh request signal producing a refresh strobe ($REF) which is applied to the first MU and which causes the means for refreshing data signals to refresh data signals stored in the addressed blocks of the first MU; the second CIU in response to the receipt of a refresh request signal producing a refresh strobe ($REF) which is applied to the second MU and which causes the means for refreshing the data signals to refresh the data signals stored in the addressed blocks of the second MU; and means for synchronizing the issuance of the refresh request and refresh address signals by the first and second clock subsystems.
Claim 3
Dependent Claim
36 words
A distributed data processing system as defined in claim 1 in which m equals two and the third and fourth circuit means applies the refresh request and refresh address signals to both sections of each MU.
Claim 4
Dependent Claim
15 words
A distributed data processing system as defined in claim 2 in which n equals eight.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-06-09 | 1989-12-09 | 1990-06-10 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-06-09 | 1993-12-09 | 1994-06-10 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-06-09 | 1997-12-09 | 1998-06-10 | $7700.00 | Window Closed / Lapsed |