High speed diode

Claim 2

A high-speed diode comprising: a semiconductor pellet including a P-layer, an N-layer, and an N + -layer so as to form a PNN + structure, the impurity concentration in the surface of said P-layer being equal to or less than 8×10 18 atoms/cc and said P-layer having a thickness of 2 to 6 μm to provide a predetermined soft reverse recovery characteristic for the diode, said N-layer having a resistivity of 5Ω-cm or more and a thickness of 19 to 25 μm, the carrier lifetime in said N-layer being in a range from 20 to 40 nanoseconds; a first electrode kept in ohmic contact with said P-layer; and a second electrode kept in ohmic contact with said N + -layer.

Claim 3

A high-speed diode according to claim 1, wherein said P-layer and said N-layer are exposed to one principal surface of said semiconductor pellet, a PN junction formed between said P-layer and N-layer terminates at said principal surface of said semiconductor pellet, said P-layer being surrounded with said N-layer at said principal surface, the terminus of said PN junction at said principal surface is coated with an insulating film, and said first electrode is extended on said insulating film so as to go beyond said terminus of said PN junction.

Claim 4

A high-speed diode according to claim 1, wherein said second electrode is bonded to said N + -layer through a semiconductor layer which has a conductivity of N-type and is larger in impurity concentration than said N + -layer.

Claim 5

A high-speed diode according to claim 1, wherein said N-layer has a resistivity of 5 to 100Ω-cm.

Claim 6

A high-speed diode according to claim 1, wherein the impurity concentration in the surface of said P-layer lies in a range from 8×10 17 to 8×10 18 atoms/cc.

Claim 7

A high-speed diode according to claim 1, wherein said semiconductor pellet is doped with a heavy metal thereby adjusting the lifetime of the minority carrier in the N-layer in the range from 20 to 40 nanoseconds.

Claim 8

A high-speed diode according to claim 1, wherein said first electrode is formed of one of a single layer of aluminum, a four layer structure of Al-Cr-Ni-Ag, a three layer structure of Cr-Ni-Ag, and a three layer structure of Ti-Ni-Ag.

Claim 9

A high-speed diode according to claim 1, wherein said N-layer has a substantially uniform resistivity.

Claim 10

A high-speed diode comprising: an n + -type low resistivity silicon substrate having mutually opposed first and second surfaces; an n-type high resistivity layer epitaxially grown on said first surface of the substrate to form a third surface, having a substantially uniform resistivity of at least 5Ω-cm and a thickness of 19 to 25 μm, and doped with lifetime killer to have a carrier lifetime of 20 to 40 nanoseconds; a p-type region diffused from the second surface into said n-type high resistivity layer and having a surface impurity concentration of at most 8×10 18 atoms/cc and a thickness of 2 to 6 μm to thereby provide a predetermined soft reverse recovery characteristic for the diode; an n ++ -type region formed in the second surface of the substrate and having a much higher surface impurity concentration than that of the p-type region; a cathode electrode formed on said n ++ -type region; and an anode electrode formed on said p-type region.

Claim 11

A high-speed diode comprising: an n + -type low resistivity silicon substrate having mutually opposed first and second surfaces; an n-type high resistivity layer epitaxially grown on said first surface of the substrate to form a third surface, having a substantially uniform resistivity of at least 5Ω-cm and a thickness of 19 to 25 μm, and doped with lifetime killer to have a carrier lifetime of 20 to 40 nanoseconds; a p-type region diffused from the second surface into said n-type high resistivity layer and having a surface impurity concentration of at most 8×10 18 atoms/cc and a thickness of 2 to 6 μm to thereby provide a predetermined soft reverse recovery characteristic for the diode; an n ++ -type region formed in the second surface of the substrate and having a much higher surface impurity concentration than that of the p-type region; a cathode electrode formed on said n ++ -type region; and an anode electrode formed on said p-type region.

Claim 12

A high-speed diode according to claim 9, wherein said impurity concentration of the p-type region is at least 8×10 17 atoms/cc to thereby suppress a contact potential difference of said anode electrode and said p-type region.

Claim 13

A high-speed diode according to claim 10, wherein said substrate is doped with antimony.