Local area network interframe delay controller

Claim 1

In data communications network having a plurality of information processing systems coupled to a communication channel which serially transmits data in the form of information packets at a first clock rate, a network controller disposed between said communication channel and an information processing system comprising: a plurality of transceivers coupled to said communication channel, each transceiver including transmitting means for transmitting a signal onto said channel, and receiving means for receiving a signal communicated on said channel by another transceiver; collision detecting means coupled to the transmitting means and the receiving means of each transceiver for generating a collision signal whenever a signal communicated on said channel by another transceiver is received by said receiving means during the time said transmitting means is transmitting a signal onto said communication channel; means connected to each transceiver and responsive to the presence of said collision signal for interrupting the transmission of a signal onto said channel by said transmitting means; means connected to each transceiver and responsive to the presence of a carrier signal on said channel for preventing the transmission of a signal by said transmitting means; an interface unit connected to said transceiver for transferring data in the form of information packets to and from said communication channel; a serializer connected to said interface unit for converting data in said information packet to be transmitted on said channel from parallel form to serial form; a transmit buffer connected to said serializer for storing in parallel form the data corresponding to a plurality of information packets to be transferred to said communication channel; a first shift register having n bit positions including a first pointer bit, circulating at a first clock rate corresponding to the clock rate of data on said communication channel, where n is an integer corresponding to the number of memory locations in said transmit buffer, the location of said pointer bit with respect to said n bit positions in said first shift register corresponding to and pointing to the memory location in said transmit buffer wherein said data from said serializer is to be transferred to said communication channel; a counter connected to said transmit buffer for controlling the release of packets from said transmit buffer according to a predetermined amount of time between the transmission of successive packets transferred from said transmit buffer to said communication channel; and mode means connected to said counter for adjusting the predetermined amount of time determined by said counter from a first fixed value to a second fixed value.