Bipolar transistor circuit with FET constant current source

Claim 2

A transistor circuit comprising: (a) a cascade connection of differential pairs of bipolar transistors, (b) a first group of FETs, each of which has a drain, a source and a gate, said FETs each being connected to a common ground-line in a common source mode, and the drain of each of said FETs being connected to the emitter of a different pair of said differential pairs of bipolar transistors, (c) bias supply means connected to the gates of said first group of FETs, (d) emitter-follower bipolar transistors inserted between adjacent differential pairs of bipolar transistors to operate as buffers between said adjacent pairs, and (e) a second group of FETs, each of which has a drain, a source and a gate, the drains of which are respectively connected to emitters of said emitter-follower bipolar transistors, and the sources of which are connected to said common ground-line, wherein said bias supply means supplies biases to the gates of said second group of FETs.

Claim 3

A transistor circuit according to claim 1, wherein said first group of FETs and said second group of FETs are enhancement-type MOSFETs.

Claim 4

A transistor circuit comprising: (a) a cascade connection of differential pairs of bipolar transistors, (b) a first group of constant current sources formed of a first group of FETs, each of which FETs has a drain, a source and a gate, said FETs each being connected to a common ground-line in a common source mode, and the drain of each of said FETS being connected to a different pair of emitters of said differential pairs of bipolar transistors, (c) bias supply means connected to the gates of said first group of FETs (d) emitter-follower bipolar transistors inserted between adjacent differential pairs of bipolar transistors to operate as buffers between said adjacent pairs, and (e) a second group of constant current sources formed of a second group of FETs, each of which has a drain, a source and a gate, the drains of which are respectively connected to emitters of said emitter-follower bipolar transistors, and the sources of which are connected to said common ground-line, wherein said bias supply means supplies biases to the gates of said second group of FETs.

Claim 5

A transistor circuit comprising: (a) a cascade connection of differential pairs of bipolar transistors, (b) a first group of constant current sources formed of a first group of FETs, each of which FETs has a drain, a source and a gate, said FETs each being connected to a common ground-line in a common source mode, and the drain of each of said FETS being connected to a different pair of emitters of said differential pairs of bipolar transistors, (c) bias supply means connected to the gates of said first group of FETs (d) emitter-follower bipolar transistors inserted between adjacent differential pairs of bipolar transistors to operate as buffers between said adjacent pairs, and (e) a second group of constant current sources formed of a second group of FETs, each of which has a drain, a source and a gate, the drains of which are respectively connected to emitters of said emitter-follower bipolar transistors, and the sources of which are connected to said common ground-line, wherein said bias supply means supplies biases to the gates of said second group of FETs.

Claim 6

A transistor circuit according to claim 3, wherein said first group of FETs and said second group of FETs are enhancement-type MOSFETS.

Claim 7

A differential amplifier integrated circuit fabricated on a single chip comprising: (a) a cascade connection of differential pairs of bipolar transistors fabricated into a differential amplifier on said chip, said bipolar transistors each having a base, an emitter and a collector with an output taken across the respective collectors of the last pair of bipolar transistors, an input coupled across the respective bases of the first pair of bipolar transistors, said bipolar transistors having output impedances; (b) a FET separately associated with each of said pairs of bipolar transistors, each FET being on said chip and having a drain, a source and a gate, each of said FETs being connected to a common ground-line and being configured in a common source mode, the drains being respectively coupled to the emitters of the associated pair of bipolar transistors; and (c) bias supply means on said chip coupled to the gate of each of said FETs to cause each FET to function as a constant current source for said associated pair of bipolar transistors, the output impedance of each of said FETs being substantially larger than the output impedance of the associated bipolar transistors whereby even number harmonics of an input signal applied to the bases of said first pair of bipolar transistors are suppressed in the output from the last pair of bipolar transistors.

Claim 8

A differential amplifier integrated circuit fabricated on a single chip comprising: (a) a cascade connection of differential pairs of bipolar transistors fabricated into a differential amplifier on said chip, said bipolar transistors each having a base, an emitter and a collector with an output taken across the respective collectors of the last pair of bipolar transistors, an input coupled across the respective bases of the first pair of bipolar transistors, said bipolar transistors having output impedances; (b) a FET separately associated with each of said pairs of bipolar transistors, each FET being on said chip and having a drain, a source and a gate, each of said FETs being connected to a common ground-line and being configured in a common source mode, the drains being respectively coupled to the emitters of the associated pair of bipolar transistors; and (c) bias supply means on said chip coupled to the gate of each of said FETs to cause each FET to function as a constant current source for said associated pair of bipolar transistors, the output impedance of each of said FETs being substantially larger than the output impedance of the associated bipolar transistors whereby even number harmonics of an input signal applied to the bases of said first pair of bipolar transistors are suppressed in the output from the last pair of bipolar transistors.

Claim 9

A differential amplifier circuit in accordance with claim 5 wherein said FETs are enhancement-type MOSFETs.

Claim 10

A differential amplifier circuit in accordance with claim 5 further comprising: (a) emitter-follower bipolar transistors on said chip inserted between adjacent differential pairs of said bipolar transistors which operate as buffers between said adjacent pairs of differential bipolar transistors; and (b) a group of FETs, each of which has a drain, a source and a gate, the drains of which are respectively connected to emitters of said emitter-follower bipolar transistors of said buffers, and the sources of which are connected to said common ground-line wherein said bias supply means supplies biases to the gates of said second group of FETs.

Claim 11

A transistor circuit according to claim 6 wherein said group of FETs are enhancement-type MOSFETs.