Multiplexer, demultiplexer and multiplexing-demultiplexing equipment with reconfigurable frames

Claim 2

A reconfigurable frame multiplexer for processing frame signals and incorporating a frame locking word, data blocks and a service block comprising: a synchronous multiplexer receiving on N inputs a number N of low flow rate channels with random flow rates and supplies a multiplexed signal on an output channel, a frame locking word insertion means located downstream of the synchronous multiplexer, a time base supplying clock and synchronization signals to the synchronous multiplexer and to the frame locking word insert means, a monitoring means for monitoring the state of the low flow rate channels and the state of the reconfigurable frame multiplexer, transmission management means applying a signal to an input of said synchronous multiplexer, said signal occupying the service block in the frame, a microprocessor provided with a random access memory and a read-only memory connected to the monitoring means, to the frame locking word insertion means, to the time base and to the transmission management means, a user interface connected to the microprocessor, the improvement being in that the time base comprises the combination of: a fast time base, two storage means, each one being able to store a frame configuration with data sent by the microprocessor, one of these storage means containing the present frame configuration, i.e. the one which is used at current time, said storage means being addressed in read-mode by the fast time base, the other storage means being addressed in write-mode by microprocessor to store a new frame configuration, a switch with two inputs and two outputs, the microprocessor being connected to one input of said switch, the fast time base to the other input of said switch, each address port of the storage means being connected to one output of said switch, said switch also having a control input controlled by the microprocessor for switching its outputs, processing means for processing the clock and synchronization signals, said processing means receiving at its input the content of the storage means read by the fast time base.

Claim 3

A multiplexer according to claim 1, wherein each storage means is a random access memory.

Claim 4

A multiplexer according to claim 1, wherein the two storage means are identical.

Claim 5

A multiplexer according to claim 1, wherein the clock and sync signal processing means comprise a decoder receiving at its input the words stored in the storage means read by the fast time base.

Claim 6

A reconfigurable frame demultiplexer, receiving frame signals incorporating a frame locking word, data blocks and a service block, said demultiplexer comprising: a synchronous demultiplexer receiving at its inputs a frame multiplexer signal and supplying at its output N component signals and an auxiliary signal, frame locking word detection means, a time base supplying clock and synchronization signals to the synchronous demultiplexer and to the frame locking word detection means, a time base supplying clock and synchronization signals to the synchronous demultiplexer and to the frame locking word detection means, a transmission management means, receiving at its input the synchronous demultiplexer auxiliary signal, a microprocessor provided with a random access memory and a read-only memory connected to the frame locking word detection means, to the time base and to the transmission management means, a user interface connected to the microprocessor, the improvement being in that the time base comprises in combination: a fast time base, two storage means, each one being able to store a frame configuration with data sent by the microprocessor, one of these storage means containing the present frame configuration, i.e. the one which is used at current time, said storage means being addressed in read-mode by the fast time base, the other storage means being addressed in write-mode by microprocessor to store a new frame configuration, a switch with two inputs and two outputs, the microprocessor being connected to one input of said switch, the fast time base to the other input of said switch, each address port of the storage means being connected to one output of said switch, said switch also having a control input controlled by the microprocessor for switching its outputs, processing means for processing clock and synchronization signals, said processing means receiving at its input the content of the storage means read by the fast time base.

Claim 7

A reconfigurable frame demultiplexer, receiving frame signals incorporating a frame locking word, data blocks and a service block, said demultiplexer comprising: a synchronous demultiplexer receiving at its inputs a frame multiplexer signal and supplying at its output N component signals and an auxiliary signal, frame locking word detection means, a time base supplying clock and synchronization signals to the synchronous demultiplexer and to the frame locking word detection means, a time base supplying clock and synchronization signals to the synchronous demultiplexer and to the frame locking word detection means, a transmission management means, receiving at its input the synchronous demultiplexer auxiliary signal, a microprocessor provided with a random access memory and a read-only memory connected to the frame locking word detection means, to the time base and to the transmission management means, a user interface connected to the microprocessor, the improvement being in that the time base comprises in combination: a fast time base, two storage means, each one being able to store a frame configuration with data sent by the microprocessor, one of these storage means containing the present frame configuration, i.e. the one which is used at current time, said storage means being addressed in read-mode by the fast time base, the other storage means being addressed in write-mode by microprocessor to store a new frame configuration, a switch with two inputs and two outputs, the microprocessor being connected to one input of said switch, the fast time base to the other input of said switch, each address port of the storage means being connected to one output of said switch, said switch also having a control input controlled by the microprocessor for switching its outputs, processing means for processing clock and synchronization signals, said processing means receiving at its input the content of the storage means read by the fast time base.

Claim 8

A demultiplexer according to claim 5, wherein each storage means is a random access memory.

Claim 9

A demultiplexer according to claim 5, wherein the two storage means are identical.

Claim 10

A demultiplexer according to claim 5, wherein the timing and sync signal processing means comprises a decoder receiving at its input the words stored in the storage means read by the fast time base.

Claim 11

A reconfigurable frame multiplexing-demultiplexing system for sending and receiving frame signals, each frame comprising a frame locking word, data blocks and a service block, said system comprising: (A) a multiplexing means comprising: a synchronous multiplexer receiving on N inputs a number N of low flow rate channels with random flow rates and supplies a multiplexed signal on an output channel, a frame locking word insertion means, located downstream of the synchronous multiplexer, a time base supplying clock and synchronization signals to the synchronous multiplexer and to the insertion frame locking word means, a monitoring means for monitoring the state of the low flow ratew channels and the state of the multiplexing means, a transmission management means applying a signal to a input of said synchronous multiplexer, said signal occupying the service block in the frame, (B) a demultiplexing means comprising: a synchronous demultiplexer receiving at its input frame a multiplexed signal and supplying at its output N component signals and an auxiliary signal, frame locking word, detection means, a time base supplying clock and synchronization signals to the synchronous demultiplexer and to the frame locking word, detection means, transmission management means, receiving at its input the synchronous demultiplexer auxiliary signal, (C) a microprocessor provided with a random access memory and a read-only memory connected to the monitoring means, the frame locking word insertion means, the time base and the transmission management mens, of the multiplexing means, to the frame locking word detection means, the time base means and the transmission management means of the demultiplexing means, (D) a user interface connected to the microprocessor, the improvement being in that each time base comprises, in combination: a fast time base, a switch with two inputs and two outputs, the microprocessor being connected to one input of said switch, the fast time base to the other input of said switch, each address port of the storage means being connected to one output of said switch, said switch also having a control input controlled by the microprocessor in order to switch the outputs, two storage means, each one being able to store a frame configuration with data sent by the microprocessor, one of these storage means containing the present frame configuration, i.e. the one which is used at current time, said storage means being addressed in read-mode by the fast time base, the other storage means being addressed in write-mode by microprocessor to store a new frame configuration, means for processing clock and synchronization signals, said processing means receiving t its input the content of the storage means read by the fast time base.

Claim 12

A reconfigurable frame multiplexing-demultiplexing system for sending and receiving frame signals, each frame comprising a frame locking word, data blocks and a service block, said system comprising: (A) a multiplexing means comprising: a synchronous multiplexer receiving on N inputs a number N of low flow rate channels with random flow rates and supplies a multiplexed signal on an output channel, a frame locking word insertion means, located downstream of the synchronous multiplexer, a time base supplying clock and synchronization signals to the synchronous multiplexer and to the insertion frame locking word means, a monitoring means for monitoring the state of the low flow ratew channels and the state of the multiplexing means, a transmission management means applying a signal to a input of said synchronous multiplexer, said signal occupying the service block in the frame, (B) a demultiplexing means comprising: a synchronous demultiplexer receiving at its input frame a multiplexed signal and supplying at its output N component signals and an auxiliary signal, frame locking word, detection means, a time base supplying clock and synchronization signals to the synchronous demultiplexer and to the frame locking word, detection means, transmission management means, receiving at its input the synchronous demultiplexer auxiliary signal, (C) a microprocessor provided with a random access memory and a read-only memory connected to the monitoring means, the frame locking word insertion means, the time base and the transmission management mens, of the multiplexing means, to the frame locking word detection means, the time base means and the transmission management means of the demultiplexing means, (D) a user interface connected to the microprocessor, the improvement being in that each time base comprises, in combination: a fast time base, a switch with two inputs and two outputs, the microprocessor being connected to one input of said switch, the fast time base to the other input of said switch, each address port of the storage means being connected to one output of said switch, said switch also having a control input controlled by the microprocessor in order to switch the outputs, two storage means, each one being able to store a frame configuration with data sent by the microprocessor, one of these storage means containing the present frame configuration, i.e. the one which is used at current time, said storage means being addressed in read-mode by the fast time base, the other storage means being addressed in write-mode by microprocessor to store a new frame configuration, means for processing clock and synchronization signals, said processing means receiving t its input the content of the storage means read by the fast time base.

Claim 13

A multiplexing-demultiplexing system according to claim 9, wherein each storage means is a random access memory.

Claim 14

A multiplexing-demultiplexing system according to claim 10, wherein the two storage means are identical.

Claim 15

A multiplexing-demultiplexing system according to claim 10, wherein each clock and sync signal processing means comprises a decoder receiving at its input the words stored in the storage means read by the fast time base.