US4587654A
Expired / Lapsed
US
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System for processing machine check interruption
Assignee: Fujitsu Ltd
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Filing: 1983-11-23
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Granted: 1986-05-06
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Expires: 2003-11-23
Abstract
Abstract A system for processing machine check interruption using a data processor which outputs a machine check interruption signal by detecting the generation of a machine check condition and which performs interruption processing on the basis of the machine check interruption signal. The data processor includes a specific code detector which detects a specific interruption signal among the machine check interruption signals, a signal converting circuit for converting the machine check interruption signal into a modified code signal when the interruption signal generated by the machine check interruption is the above-mentioned specific code, and a control portion which assumes a disabled-waiting condition in response to the modified code signal. The operation of the data processor is stopped by placing the control portion in a disabled-waiting condition when interruption of the above-mentioned specific code occurs.
Inventors
- 👤 Toshio Matsumoto
- 👤 Motokazu Kato
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 18:47
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/07; G06F11/0703; G06F11/0706; G06F11/0721; G06F11/0751; G06F11/0793
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
145 words
A system for processing machine check interruption, including a data processor which acts upon machine check interruption signals, the data processor detecting the generation of a machine check condition and performing interruption processing on the basis of the machine check interruption signals, said data processor comprising: specific code detector means, operatively connected to receive the machine check interruption signals, for detecting a specific interruption signal among the machine check interruption signals; signal converting means, operatively connected to said specific code detector means, for converting the machine check interruption signals into modified code signals when the specific interruption signal is detected by said specific code detector; and a control portion, operatively connected to said signal converting means, for assuming a disabled-waiting condition in response to the modified code signals, the operation of said data processor being stopped by placing said control portion in the disabled-waiting condition.
Claim 2
Independent Claim
145 words
A system for processing machine check interruption, including a data processor which acts upon machine check interruption signals, the data processor detecting the generation of a machine check condition and performing interruption processing on the basis of the machine check interruption signals, said data processor comprising: specific code detector means, operatively connected to receive the machine check interruption signals, for detecting a specific interruption signal among the machine check interruption signals; signal converting means, operatively connected to said specific code detector means, for converting the machine check interruption signals into modified code signals when the specific interruption signal is detected by said specific code detector; and a control portion, operatively connected to said signal converting means, for assuming a disabled-waiting condition in response to the modified code signals, the operation of said data processor being stopped by placing said control portion in the disabled-waiting condition.
Claim 3
Dependent Claim
45 words
A system according to claim 1, wherein said data processor comprises a memory control unit having a signal generating portion, and wherein the specific interruption signal is generated when the machine check condition is detected by the signal generating portion of said memory control unit.
Claim 4
Dependent Claim
16 words
A system according to claim 1, wherein said modified code signals comprise an all "0" code.
Claim 5
Independent Claim
148 words
A method for processing machine check interruption under the control of a data processor which detects the generation of a machine check condition and then performs interruption processing in accordance with the machine check interruption signals, the data processor including a central processing unit, a memory control unit which outputs machine check interruption signals and a main storage unit, said method comprising the steps of: (a) detecting a fault in the central processing unit and the memory control unit and generating respective machine check interruption signals; (b) generating, in the central processing unit, a modified machine check interruption code in response to the machine check interruption signals generated in step (a); (c) storing the modified machine check interruption code and a machine check processing routine in the control portion in the main storage unit and issuing a disabled-waiting condition in accordance with the modified machine check interruption code.
Claim 6
Independent Claim
148 words
A method for processing machine check interruption under the control of a data processor which detects the generation of a machine check condition and then performs interruption processing in accordance with the machine check interruption signals, the data processor including a central processing unit, a memory control unit which outputs machine check interruption signals and a main storage unit, said method comprising the steps of: (a) detecting a fault in the central processing unit and the memory control unit and generating respective machine check interruption signals; (b) generating, in the central processing unit, a modified machine check interruption code in response to the machine check interruption signals generated in step (a); (c) storing the modified machine check interruption code and a machine check processing routine in the control portion in the main storage unit and issuing a disabled-waiting condition in accordance with the modified machine check interruption code.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-05-05 | 1989-11-04 | 1990-05-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-05-05 | 1993-11-04 | 1994-05-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-05-05 | 1997-11-04 | 1998-05-06 | $7700.00 | Window Closed / Lapsed |