Apparatus for generating the magnitude of the vector sum of two orthogonal signals as for use in a digital TV receiver

Claim 2

Apparatus for generating magnitude values, C, of the vector sum of component signal vectors A and B comprising: means for applying signal vectors A and B; means for generating signals corresponding to the angles θ of said vector sum relative to the axis of one of said signal vectors A and B; means responsive to said θ signals for generating signals corresponding to values K; means responsive to the signal vectors A and B for determining the signal vector A or B having the lessor magnitude; means responsive to the signal corresponding to the values K for weighting the signal vector A or B having the lessor magnitude, by the factor K; and means for summing the weighted signal with the signal corresponding to the signal vectors A or B having the greater magnitude, the output of the summing circuit being substantially equal to the magnitude of the vector sum.

Claim 3

The apparatus set forth in claim 1 wherein the means for generating signals corresponding to values, K is a ROM having an address input port coupled to said means for generating signals corresponding to angles θ, and programmed to output said values corresponding to K responsive to angle values, θ, applied as address codes, and wherein the values K are developed from at least one of the expression (1-cos θ)/sin θ and (1-sin θ)/cos θ.

Claim 4

Apparatus for generating the magnitude values of the vector sums of two component vectors comprising: a source of signals corresponding to said two component vectors; a source of angle values corresponding to the angle between said vector sum and the axis of one of said two component vectors; means responsive to said angle values for generating coefficient values, K, related to said angle values; means responsive to said values K for weighting signals applied thereto; a summing circuit having a first input port coupled to said weighting means, having a second port and an output port; means for coupling one of said two component vector signals from said source to the second input port of said summing circuit and the other of said two component vector signals to said weighting means; and wherein signal values, C, produced at the output port of said summing circuit represent the magnitude values of the vector sum of said two component vector signals.

Claim 5

Apparatus for generating the magnitude values of the vector sums of two component vectors comprising: a source of signals corresponding to said two component vectors; a source of angle values corresponding to the angle between said vector sum and the axis of one of said two component vectors; means responsive to said angle values for generating coefficient values, K, related to said angle values; means responsive to said values K for weighting signals applied thereto; a summing circuit having a first input port coupled to said weighting means, having a second port and an output port; means for coupling one of said two component vector signals from said source to the second input port of said summing circuit and the other of said two component vector signals to said weighting means; and wherein signal values, C, produced at the output port of said summing circuit represent the magnitude values of the vector sum of said two component vector signals.

Claim 6

The apparatus set forth in claim 3 wherein the means for coupling said source to said summing circuit and said weighting means includes at least one absolute value circuit coupled between said source and said summing and weighting means for providing only the magnitudes of said two component vector signals.

Claim 7

The apparatus set forth in claim 4 wherein the means for coupling said source to said summing circuit and said weighting means further includes: means coupled to said at least one absolute value circuit for generating a control signal having a first state for the magnitude of said one of said two component vector signals being greater than the magnitude of said other of said two component vector signals and having a second state otherwise; switch means responsive to said control signal for coupling the absolute values of the one of the two component vector signals having the larger magnitude to the second input of the summing circuit and the absolute values of the other of the two component vector signals to the weighting means.

Claim 8

The apparatus set forth in claim 5 wherein the weighting means comprises a shift and add circuit and the coefficient values K are in the form of bit-shift control signals.

Claim 9

The apparatus set forth in claim 5 wherein the means for generating the coefficient values K is a ROM having an address input port coupled to said source of angle values and programmed to output values K responsive to said angle values applied as address codes and wherein the values K are symmetric about a predetermined angle value.

Claim 10

The apparatus set forth in claim 3 wherein the weighting means comprises a shift and add circuit having a signal input port coupled to said means for coupling, having a control input port coupled to said means for generating coefficients, and wherein the coefficient values, K, are in the form of bit-shift control signals.

Claim 11

The apparatus set forth in claim 3 wherein the means for generating the coefficient values, K, is a ROM having an address input port coupled to said source of angle values, and programmed to output values K responsive to said angle values applied thereto as address codes.

Claim 12

The apparatus set forth in claim 9 wherein the ROM for generating coefficient values K is programmed to produce like values of K for predetermined ranges of angles values.

Claim 13

The apparatus set forth in claim 3 wherein the means for generating coefficient values K produces like values of K for predetermined ranges of angles values.

Claim 14

The apparatus set forth in claim 3 wherein the means for generating the coefficient values, K, is a ROM having an address input port coupled to said source of angle values, and programmed to output values K responsive to said angle values applied thereto as address codes and wherein the values K are developed from at least one of the expressions (1-cos θ)/sin θ and (1-sin θ)/cos θ where θ corresponds to the angle values.

Claim 15

Apparatus for generating the magnitude values, C, of the vector sum of two substantially orthogonal vector signals I and Q comprising: means for applying said vector signals I and Q; means responsive to said I and Q vectors for generating the angle, θ, between the vector sum of the vectors I and Q and the axis of one of the I and Q vectors; means responsive to the angles θ for generating signal values, corresponding to coefficients K; an adder circuit having first and second input ports and an output port; weighting means having a first input port coupled to said means for generating values, K, having a second input port for applying signal values and having an output port; means for coupling the output port of said weighting means to the first input port of said adder circuit; means for coupling the I vector signals to the second input port of said adder circuit; means for coupling the Q vector signals to the second input port of said weighting circuit; and wherein the values available at the output port are equal to the sums I+KQ at least over a range of values θ, and the sums I+KQ approximates the magnitude, C, of the vector sum of I and Q.

Claim 16

Apparatus for generating the magnitude values, C, of the vector sum of two substantially orthogonal vector signals I and Q comprising: means for applying said vector signals I and Q; means responsive to said I and Q vectors for generating the angle, θ, between the vector sum of the vectors I and Q and the axis of one of the I and Q vectors; means responsive to the angles θ for generating signal values, corresponding to coefficients K; an adder circuit having first and second input ports and an output port; weighting means having a first input port coupled to said means for generating values, K, having a second input port for applying signal values and having an output port; means for coupling the output port of said weighting means to the first input port of said adder circuit; means for coupling the I vector signals to the second input port of said adder circuit; means for coupling the Q vector signals to the second input port of said weighting circuit; and wherein the values available at the output port are equal to the sums I+KQ at least over a range of values θ, and the sums I+KQ approximates the magnitude, C, of the vector sum of I and Q.

Claim 17

The apparatus set forth in claim 13 wherein the means for coupling the I signal vectors to the adder circuit and for coupling the Q signal vectors to the weighting means includes: means responsive to the I and Q signals for generating a control signal when the magnitude of the I signal vector exceeds the magnitude of the Q signal vector; switch means having input ports for applying the I and Q signal vectors and having a first output port coupled to the second input of the adder circuit and a second output port coupled to the second input of the weighting means, said switch means coupling the I and Q signal vectors to its first and second output ports respectively responsive to said control signal and coupling the I and Q signal vectors to its second and first output ports otherwise.

Claim 18

The apparatus set forth in claim 14 wherein the means for coupling the I signal vectors to the adder circuit and for coupling the Q signal vectors to the weighting means further includes means coupled between the means for applying the I and Q signal vectors and the adder circuit and weighting means for converting the I and Q signal vectors to signals corresponding to their magnitudes only.

Claim 19

A TV receiver having a color correction circuitry of the type which performs color correction by effectively rotating the chrominance vector, said circuitry operating on first and second substantially orthogonal color mixture signals and including means for calculating the magnitude and angle of the vector sum of said first and second color mixture signals, said color correction circuitry improved by having simplified magnitude calculating means wherein the improved magnitude calculating means comprises: means for producing the absolute values of the first and second color mixture signals; means responsive to the calculated angles for generating signals corresponding to values, K; means for predetermining the first and second color mixture signal having the lessor magnitude; means responsive to the signals corresponding to values, K, for weighting the absolute value of the first and second color mixture signal of lessor magnitude; means for summing the weighted color mixture signal with the absolute value of the other non-weighted color mixture signal, the output of the summing means approximating the magnitude of the chrominance signal.

Claim 20

A TV receiver having a color correction circuitry of the type which performs color correction by effectively rotating the chrominance vector, said circuitry operating on first and second substantially orthogonal color mixture signals and including means for calculating the magnitude and angle of the vector sum of said first and second color mixture signals, said color correction circuitry improved by having simplified magnitude calculating means wherein the improved magnitude calculating means comprises: means for producing the absolute values of the first and second color mixture signals; means responsive to the calculated angles for generating signals corresponding to values, K; means for predetermining the first and second color mixture signal having the lessor magnitude; means responsive to the signals corresponding to values, K, for weighting the absolute value of the first and second color mixture signal of lessor magnitude; means for summing the weighted color mixture signal with the absolute value of the other non-weighted color mixture signal, the output of the summing means approximating the magnitude of the chrominance signal.

Claim 21

The apparatus set forth in claim 16 wherein the means for generating signals corresponding to values, K is a ROM having an input address port coupled to said means for calculating angles, and programmed to output said values corresponding to K responsive to angle values, θ, applied as address codes, and wherein the values K are developed from at least one of the expression (1-cos θ)/sin θ and (1-sin θ)/cos θ.