US4587443A
Expired / Lapsed
US
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Auto-zero sample and hold circuit
Assignee: Signetics Corp
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Filing: 1984-08-27
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Granted: 1986-05-06
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Expires: 2004-08-27
Abstract
Abstract A sample and hold circuit contains a pair of differential amplifiers (A1 and A2) switchably arranged in series. The circiut input signal (V IN ) during sample is provided to the first amplifier (A1) which is coupled to a storage capacitor (C). The second amplifier (A2) provides the circuit output signal (V OUT ) during hold. Switching circuitry (S1, S2, and S3) enables the input and output signals to undergo the same transfer function in the first amplifier. The voltage offset of the first amplifier is thereby cancelled out of the output signal, while the effect of the voltage offset of the second amplifier is reduced drastically so as to provide excellent auto-zeroing.
Inventors
- 👤 Rudy J. VAN DE Plassche
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 09:13
CPC Classifications
G; G11; G11C; G11C27/00; G11C27/02; G11C27/024; G11C27/026
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
182 words
A sample and hold circuit comprising: first means for amplifying a differential signal between non-inverting and inverting inputs thereof to produce a differential signal between non-inverting and inverting outputs thereof; second means for amplifying a differential signal between non-inverting and inverting inputs thereof to produce a signal at an output thereof: a storage capacitor coupled to the inverting input of the first means: a first switch for selectively coupling the non-inverting input of the first means to a circuit input terminal for receiving an input signal during a sample mode or to the output of the second means during a hold mode; a second switch for selectively coupling the output of the second means to the inverting input of the first means during the sample mode or to a high-impedance position during the hold mode; and a third switch for selectively coupling the non-inverting and inverting outputs of the first means respectively to the non-inverting and inverting inputs of the second means during the sample mode or respectively to the inverting and non-inverting inputs of the second means during the hold mode.
Claim 2
Dependent Claim
182 words
A sample and hold circuit comprising: first means for amplifying a differential signal between non-inverting and inverting inputs thereof to produce a differential signal between non-inverting and inverting outputs thereof; second means for amplifying a differential signal between non-inverting and inverting inputs thereof to produce a signal at an output thereof: a storage capacitor coupled to the inverting input of the first means: a first switch for selectively coupling the non-inverting input of the first means to a circuit input terminal for receiving an input signal during a sample mode or to the output of the second means during a hold mode; a second switch for selectively coupling the output of the second means to the inverting input of the first means during the sample mode or to a high-impedance position during the hold mode; and a third switch for selectively coupling the non-inverting and inverting outputs of the first means respectively to the non-inverting and inverting inputs of the second means during the sample mode or respectively to the inverting and non-inverting inputs of the second means during the hold mode.
Claim 3
Dependent Claim
25 words
A circuit as in claim 1 wherein the capacitor is particularly connected between a supply voltage point and the inverting input of the first means.
Claim 4
Dependent Claim
30 words
A circuit as in claim 1 wherein the signal at the output of the second means is substantially an output signal of the circuit during at least the hold mode.
Claim 5
Dependent Claim
21 words
A circuit as in claim 3 wherein the output signal is substantially independent of the voltage offset of the first means.
Claim 6
Dependent Claim
54 words
A circuit as in claim 4 wherein V.sub.OUT ≈(1-2/A.sub.1 A.sub.2)V.sub.IN +2V.sub.OS2 /A.sub.1 where V OUT and V IN are the respective voltages of the output and input signals, A 1 and A 2 are the respective gains of the first and second means, and V OS2 is the voltage offset of the second means.
Claim 7
Dependent Claim
15 words
A circuit as in claim 1 wherein each switch comprises at least one field-effect transistor.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-05-05 | 1989-11-04 | 1990-05-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-05-05 | 1993-11-04 | 1994-05-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-05-05 | 1997-11-04 | 1998-05-06 | $7700.00 | Window Closed / Lapsed |