US4586129A
Expired / Lapsed
US
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Apparatus and method for testing and verifying the timing logic of a cathode ray tube display
Assignee: Bull HN Information Systems Inc
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Filing: 1983-07-05
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Granted: 1986-04-29
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Expires: 2003-07-05
Abstract
Abstract A data processing system includes a cathode ray tube (CRT) display. Apparatus associated with the CRT tests and verifies the vertical and horizontal synchronization and the logic associated with a character generator. Refresh signals, horizontal synchronization signals and data bit signals from the character generator are counted. The counts of those signals which occur within a predetermined number of occurrences of vertical synchronization signals are verified.
Inventors
- 👤 Thomas L. Murray, Jr.
- 👤 Kin C. Yu
- 👤 Thomas O. Holtey
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 00:45
CPC Classifications
G; G06; G06F; G06F3/00; G06F3/14; G06F3/153; G09; G09G; G09G3/00; G09G3/006; G01; G01R; G01R31/00; G01R31/28; G01R31/2832; G01R31/2834; G06F11/00; G06F11/07; G06F11/0703; G06F11/0751; G06F11/0754; G06F11/0757
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
184 words
A method of verifying the correct synchronization of a cathode ray tube (CRT) display subsystem of a data processing system, said data processing system including an I/O microprocessor, a dynamic random access memory (RAM) which is periodically refreshed and said CRT display subsystem, said method comprising the steps of: (a) generating vertical synchronization signals in said CRT display subsystem; (b) interrupting said I/O microprocessor by a first occurrence of said vertical synchronization signals; (c) by said I/O microprocessor generating a plurality of control signals in a first state for selecting as an input to a counter a refresh signal which refreshes addressed locations of said RAM; (d) by said counter, counting the number of said refresh signals; (e) interrupting said I/O microprocessor by a subsequent occurrence of a vertical synchronization signal; (f) reading out the count of said refresh signals when said I/O microprocessor has been interrupted by a predetermined number of occurrences of said vertical synchronization signals; and (g) verifying that the count of said refresh signals is within a first predetermined range thereby indicating that said vertical synchronization cycle timing is correct.
Claim 2
Independent Claim
184 words
A method of verifying the correct synchronization of a cathode ray tube (CRT) display subsystem of a data processing system, said data processing system including an I/O microprocessor, a dynamic random access memory (RAM) which is periodically refreshed and said CRT display subsystem, said method comprising the steps of: (a) generating vertical synchronization signals in said CRT display subsystem; (b) interrupting said I/O microprocessor by a first occurrence of said vertical synchronization signals; (c) by said I/O microprocessor generating a plurality of control signals in a first state for selecting as an input to a counter a refresh signal which refreshes addressed locations of said RAM; (d) by said counter, counting the number of said refresh signals; (e) interrupting said I/O microprocessor by a subsequent occurrence of a vertical synchronization signal; (f) reading out the count of said refresh signals when said I/O microprocessor has been interrupted by a predetermined number of occurrences of said vertical synchronization signals; and (g) verifying that the count of said refresh signals is within a first predetermined range thereby indicating that said vertical synchronization cycle timing is correct.
Claim 3
Dependent Claim
137 words
The method of claim 1 further comprising the steps of: (a) generating horizontal synchronization signals; (b) interrupting said I/O microprocessor by a first occurrence of said vertical synchronization signals; (c) by said I/O microprocessor generating said plurality of control signals in a second state for selecting as an input to said counter said horizontal synchronization signals; (d) by said counter counting the number of said horizontal synchronization signals; (e) interrupting said I/O microprocessor by a subsequent occurrence of said vertical synchronization signal; (f) reading out the count of said horizontal synchronization signals when said I/O microprocessor has been interrupted by a predetermined number of occurrences of said vertical synchronization signals; and (g) verifying that the count of said horizontal synchronization signals is within a second predetermined range thereby indicating that said horizontal synchronization cycle timing is correct.
Claim 4
Dependent Claim
163 words
The method of claim 2 further comprising the steps of: (a) generating said data bit signals, successive occurrences of said data bit signals being indicative of a predetermined display on the screen of said CRT; (b) interrupting said I/O microprocessor by a first occurrence of said vertical synchronization signals; (c) by said I/O microprocessor generating said plurality of control signals in a third state for selecting as an input to said counter said data bit signal; (d) by said counter counting the number of occurrences of said data bit signals; (e) interrupting said I/O microprocessor by a subsequent occurrence of said vertical synchronization signals; (f) reading out the count of said data bit signals when said I/O microprocessor has been interrupted by a predetermined number of occurrences of said vertical synchronization signals; and (g) verifying that the count of said number of occurrences of said data bit signals is within a third predetermined range thereby indicating that said data bit timing is correct.
Claim 5
Dependent Claim
189 words
A data processing system includes a dynamic random access memory (RAM), an input/output microprocessor and cathode ray tube display terminal (CRT), all coupled in common to a system bus, said data processing system including apparatus for testing and verifying the timing of the CRT, said apparatus comprising: first means for generating vertical synchronization signals; second means for generating refresh signals for refreshing said RAM; means including the I/O microprocessor responsive to a first occurrence of said vertical synchronization signals for generating a plurality of control signals in a first state; and counter means responsive to said plurality of control signals in said first state for selecting as an input said refresh signals and having means for storing a first count of the number of occurrences of said refresh signals received by said counter means; said I/O microprocessor having means for storing a second count of the number of subsequent occurrences of said vertical synchronization signals and having means for verifying that said first count is within a first predetermined range when said second count is equal to a predetermined count thereby verifying the timing of said vertical synchronization cycle.
Claim 6
Dependent Claim
189 words
A data processing system includes a dynamic random access memory (RAM), an input/output microprocessor and cathode ray tube display terminal (CRT), all coupled in common to a system bus, said data processing system including apparatus for testing and verifying the timing of the CRT, said apparatus comprising: first means for generating vertical synchronization signals; second means for generating refresh signals for refreshing said RAM; means including the I/O microprocessor responsive to a first occurrence of said vertical synchronization signals for generating a plurality of control signals in a first state; and counter means responsive to said plurality of control signals in said first state for selecting as an input said refresh signals and having means for storing a first count of the number of occurrences of said refresh signals received by said counter means; said I/O microprocessor having means for storing a second count of the number of subsequent occurrences of said vertical synchronization signals and having means for verifying that said first count is within a first predetermined range when said second count is equal to a predetermined count thereby verifying the timing of said vertical synchronization cycle.
Claim 7
Dependent Claim
116 words
The apparatus of claim 4 wherein: said I/O microprocessor includes means responsive to a first occurrence of said vertical synchronization signals for generating said plurality of control signals in a second state; said counter means includes means responsive to said plurality of control signals in said second state for selecting as an input said horizontal synchronization signals and includes means for storing a third count of the number of occurrences of said horizontal synchronization signals received by said counter means; said I/O microprocessor includes means for verifying that said third count is within a second predetermined range when said second count is equal to a predetermined count thereby verifying the timing of said horizontal synchronization cycle.
Claim 8
Dependent Claim
112 words
The apparatus of claim 5 further comprising means for generating data bit signals and wherein: said I/O microprocessor includes means responsive to a first occurrence of said vertical synchronization signals for generating said plurality of control signals in a third state; said counter means includes means responsive to said plurality of control signals in said third state for selecting as an input said data bit signals and includes means for storing a fourth count of the number of occurrences of said data bit signal received by said counter means; said I/O microprocessor includes means for verifying that said second count is equal to a predetermined count thereby verifying said data bit timing.
Claim 9
Dependent Claim
11 words
The apparatus of claim 6 wherein said second count is two.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-04-28 | 1989-10-28 | 1990-04-29 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-04-28 | 1993-10-28 | 1994-04-29 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-04-28 | 1997-10-28 | 1998-04-29 | $7700.00 | Window Closed / Lapsed |