US4585952A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Digital waveform shaping circuit
Assignee: Sansui Electric Co Ltd
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Filing: 1983-03-04
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Granted: 1986-04-29
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Expires: 2003-03-04
Abstract
Abstract The present invention provides a digital signal waveform shaping circuit for reproducing a digital signal recorded on a recording medium. The waveform shaping circuit includes at least one comparator for receiving an input signal and a delay circuit connected to the output of the comparator for delaying the comparator output by one-bit-cell. The input signal is compared with a threshold level associated with the output of the delay circuit.
Inventors
- 👤 Takaaki Yamamoto
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 22:07
CPC Classifications
G; G11; G11B; G11B20/00; G11B20/10; G11B20/10527; G11B20/10009; H; H03; H03K; H03K5/00; H03K5/01; H03K5/08; H03K5/082; H03K5/086
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
161 words
In a device for reproducing a digital signal recorded on a recording medium, a digital signal waveform shaping circuit comprising, at least one comparator having a first input for receiving an input signal corresponding to said digital signal and a second input for receiving a threshold level signal, a delay circuit comprising at least one pair of cascade connected flip-flops, an input to the first flip-flop of said at least one pair of flip-flops being connected to the output of said at least one comparator, the second input of said comparator being responsive to the output of the second flip-flop of said at least one pair of flip-flops, synchronizing signal means for producing synchronizing signals to clock said first and second flip-flops of said at least one pair of flip-flops, first means for applying said synchronizing signals to the clock input of said first flip-flop and second means for applying inverted synchronizing signals to the clock input of said second flip-flop.
Claim 2
Dependent Claim
161 words
In a device for reproducing a digital signal recorded on a recording medium, a digital signal waveform shaping circuit comprising, at least one comparator having a first input for receiving an input signal corresponding to said digital signal and a second input for receiving a threshold level signal, a delay circuit comprising at least one pair of cascade connected flip-flops, an input to the first flip-flop of said at least one pair of flip-flops being connected to the output of said at least one comparator, the second input of said comparator being responsive to the output of the second flip-flop of said at least one pair of flip-flops, synchronizing signal means for producing synchronizing signals to clock said first and second flip-flops of said at least one pair of flip-flops, first means for applying said synchronizing signals to the clock input of said first flip-flop and second means for applying inverted synchronizing signals to the clock input of said second flip-flop.
Claim 3
Dependent Claim
25 words
The digital signal waveform shaping circuit according to claim 1, wherein the output of said comparator is connected to the waveform shaping circuit output terminal.
Claim 4
Dependent Claim
81 words
The digital signal waveform shaping circuit according to claim 1, wherein said delay circuit comprises a plurality of pairs of cascade connected flip-flops, said waveform shaping circuit further including decoder means responsive to the outputs of the second flip-flop of each pair of cascade connected flip-flops, a plurality of threshold level voltage sources, and selector means for selectively connecting said threshold level voltage sources to said comparator threshold level signal input terminal in response to the output of said decoder means.
Claim 5
Dependent Claim
27 words
The digital signal waveform shaping circuit according to claim 3, wherein said decoder means comprises an n-bit decoder, and said selector means selects 2 n threshold voltages.
Claim 6
Dependent Claim
66 words
The digital signal waveform shaping circuit according to claim 1, wherein said delay circuit comprises a plurality of pairs of cascade connected flip-flops, said waveform shaping circuit further comprising a digital-to-analog converter means, responsive to the outputs of the second flip-flops of each pair of cascade connected flip-flops, the threshold level signal input of said comparator being responsive to the output of said digital-to-analog converter means.
Claim 7
Dependent Claim
116 words
A digital signal waveform shaping circuit comprising, at least one comparator, a delay circuit, and means for applying an input signal corresponding to said digital signal to a first input of said comparator and to the input of said delay circuit, the output of said delay circuit being connected to a second input of said comparator, said delay circuit comprising a plurality of bit delay means each connected to the delay circuit input for receiving the input signal and each delaying an input bit thereto by one bit cell more than its immediately preceding bit delay means, the delay circuit further comprising an adder circuit responsive to the outputs of said plurality of bit delay means.
Claim 8
Dependent Claim
116 words
A digital signal waveform shaping circuit comprising, at least one comparator, a delay circuit, and means for applying an input signal corresponding to said digital signal to a first input of said comparator and to the input of said delay circuit, the output of said delay circuit being connected to a second input of said comparator, said delay circuit comprising a plurality of bit delay means each connected to the delay circuit input for receiving the input signal and each delaying an input bit thereto by one bit cell more than its immediately preceding bit delay means, the delay circuit further comprising an adder circuit responsive to the outputs of said plurality of bit delay means.
Claim 9
Dependent Claim
87 words
In a device for reproducing a digital signal recorded on a recording medium, a digital signal waveform shaping circuit comprising, at least one comparator having a first input for receiving an input signal corresponding to said digital signal and a second input for receiving a threshold level signal, and delay means comprising a flip-flop responsive to the output of said comparator and an integrator means for integrating the flip-flop output, the output of the integrator means being connected to the threshold level signal input of said comparator.
Claim 10
Dependent Claim
87 words
In a device for reproducing a digital signal recorded on a recording medium, a digital signal waveform shaping circuit comprising, at least one comparator having a first input for receiving an input signal corresponding to said digital signal and a second input for receiving a threshold level signal, and delay means comprising a flip-flop responsive to the output of said comparator and an integrator means for integrating the flip-flop output, the output of the integrator means being connected to the threshold level signal input of said comparator.
Claim 11
Dependent Claim
125 words
In a device for reproducing a digital signal recorded on a recording medium, a digital signal waveform shaping circuit comprising, at least one comparator having a first input for receiving an input signal corresponding to said digital signal and a second input for receiving a threshold level signal, at least one pair of cascade connected flip-flops, an input to the first flip-flop of said at least one pair of flip-flops being connected to the output of said comparator, the output of the second flip-flop of the at least one pair of flip-flops being connected through an inverter to the input of said comparator receiving said input signal, said threshold level signal receiving input of said comparator being connected to a fixed threshold level signal source.
Claim 12
Dependent Claim
125 words
In a device for reproducing a digital signal recorded on a recording medium, a digital signal waveform shaping circuit comprising, at least one comparator having a first input for receiving an input signal corresponding to said digital signal and a second input for receiving a threshold level signal, at least one pair of cascade connected flip-flops, an input to the first flip-flop of said at least one pair of flip-flops being connected to the output of said comparator, the output of the second flip-flop of the at least one pair of flip-flops being connected through an inverter to the input of said comparator receiving said input signal, said threshold level signal receiving input of said comparator being connected to a fixed threshold level signal source.
Claim 13
Dependent Claim
112 words
A digital signal waveform shaping circuit comprising a first comparator receiving a higher threshold level, a second comparator receiving a lower threshold level and a third comparator receiving a threshold level between said higher and lower levels, one input of the respective comparators receiving an input signal corresponding to said digital signal, a frist delay circuit connected to the output of said first comparator, a second delay circuit connected to the output of said second comparator, a selector means for selecting one of the outputs of the comparators based on the preceding data delivered from said first and second delay circuits, and a flip-flop connected to the output of said selector means.
Claim 14
Dependent Claim
112 words
A digital signal waveform shaping circuit comprising a first comparator receiving a higher threshold level, a second comparator receiving a lower threshold level and a third comparator receiving a threshold level between said higher and lower levels, one input of the respective comparators receiving an input signal corresponding to said digital signal, a frist delay circuit connected to the output of said first comparator, a second delay circuit connected to the output of said second comparator, a selector means for selecting one of the outputs of the comparators based on the preceding data delivered from said first and second delay circuits, and a flip-flop connected to the output of said selector means.
Claim 15
Dependent Claim
35 words
The digital signal waveform shaping circuit according to claim 9, wherein the outputs of the plural comparators are selected in accordance with the preceding data transmitted from the delay circuits respectively connected to said comparators.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-04-28 | 1989-10-28 | 1990-04-29 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-04-28 | 1993-10-28 | 1994-04-29 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-04-28 | 1997-10-28 | 1998-04-29 | $7700.00 | Window Closed / Lapsed |