← Back to Patent Explorer
US4585515A Expired / Lapsed US ⏱️ 0.0 years remaining

Formation of conductive lines

Assignee: Intersil Corp
•
Filing: 1985-03-11
•
Granted: 1986-04-29
•
Expires: 2005-03-11
📄 Original PDF 🌐 Google Patents 🔄 Sync Now

Abstract

Abstract A process of forming conductive lines of fine dimensions over a substrate having topographical features without the formation of conductive stringers is disclosed. Openings of the desired dimensions overlying the topographical features are lithographically defined in a layer of planarizing dielectric material deposited on the substrate. A layer of doped silicon is deposited thereover and isotropically etched to remove all except for the portion in the openings in the dielectric layer. A layer of metal is deposited to overlie only the silicon in the openings in the dielectric layer. The structure is annealed to convert the metal to metal silicide and the remaining dielectric layer is removed.

Inventors

  • 👤 Jer-shen Maa

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-28 14:23
CPC Classifications
H; H10; H10P; H10P50/00; H10P50/20; H10P50/28; H10P50/282; H10P50/283; H10D; H10D64/00; H10D64/01; H10D64/011; H10D64/013; H10D64/01302; H10D64/01304; H10D64/01306; H10D64/01308; H10D64/0131; H10W; H10W20/00; H10W20/01; H10W20/031; H10W20/062; H10W20/064; H10W20/066

Claims Analysis

Total Claims: 13
Claim 1
Independent Claim 132 words
A process of forming conductive lines on a substrate having topographical features comprising: (a) depositing a layer of planarizing dielectric material on the substrate; (b) forming a patterned layer of resist material over the layer of dielectric material wherein the exposed portion of the dielectric layer overlies topographical features on the substrate; (c) etching away the exposed dielectric layer; (d) removing the remaining resist layer; (e) depositing a layer of doped silicon over the structure; (f) isotropically etching the silicon layer thereby removing it from the surface of the dielectric layer leaving only a portion thereof in the openings in the dielectric layer; (g) depositing a metal to overlie the silicon in said openings; (h) annealing the structure to convert the metal to metal silicide; and (i) removing the remaining dielectric layer.
Claim 2
Dependent Claim 132 words
A process of forming conductive lines on a substrate having topographical features comprising: (a) depositing a layer of planarizing dielectric material on the substrate; (b) forming a patterned layer of resist material over the layer of dielectric material wherein the exposed portion of the dielectric layer overlies topographical features on the substrate; (c) etching away the exposed dielectric layer; (d) removing the remaining resist layer; (e) depositing a layer of doped silicon over the structure; (f) isotropically etching the silicon layer thereby removing it from the surface of the dielectric layer leaving only a portion thereof in the openings in the dielectric layer; (g) depositing a metal to overlie the silicon in said openings; (h) annealing the structure to convert the metal to metal silicide; and (i) removing the remaining dielectric layer.
Claim 3
Dependent Claim 17 words
A process in accordance with claim 1, wherein the substrate is sapphire having silicon topographical features thereon.
Claim 4
Dependent Claim 15 words
A process in accordance with claim 1, wherein the planarizing dielectric material is silicon dioxide.
Claim 5
Dependent Claim 21 words
A process in accordance with claim 3, wherein the dielectric layer is plasma etched with a mixture of trifluoromethane and hydrogen.
Claim 6
Dependent Claim 54 words
A process in accordance with claim 1, wherein the doped silicon layer is deposited in the amorphous state by low pressure chemical vapor deposition from a source of silicon and a suitable dopant at a temperature of from about 560° to 580° C. and the annealing step converts said layer to the polycrystalline state.
Claim 7
Dependent Claim 19 words
A process in accordance with claim 5, wherein the source of silicon is silane and the dopant is phosphine.
Claim 8
Dependent Claim 23 words
A process in accordance with claim 1, wherein the silicon layer is isotropically plasma etched with a mixture of carbon tetrafluoride and oxygen.
Claim 9
Dependent Claim 23 words
A process in accordance with claim 1, wherein the metal is selected from the group consisting of tungsten, tantalum, titanium, niobium and molybdenum.
Claim 10
Dependent Claim 12 words
A process in accordance with claim 8, wherein the metal is tungsten.
Claim 11
Dependent Claim 37 words
A process in accordance with claim 9, wherein the dielectric material is silicon dioxide and tungsten is selectively deposited on the silicon in said openings by chemical vapor deposition from a mixture of tungsten hexafluoride and hydrogen.
Claim 12
Dependent Claim 12 words
A process in accordance with claim 8, wherein the metal is tantalum.
Claim 13
Dependent Claim 40 words
A process in accordance with claim 1, wherein the metal is deposited over the surface of the structure formed in step (f) and said metal layer is isotropically etched to leave only that portion overlying the silicon in said openings.

References Cited (Backward Citations)

US4410622A Cited
US4411734A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1989-04-28 1989-10-28 1990-04-29 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1993-04-28 1993-10-28 1994-04-29 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1997-04-28 1997-10-28 1998-04-29 $7700.00 Window Closed / Lapsed

Assigned Categories & Tags

No categories assigned to this patent yet.

Assign Category Tag