Floating point/logarithmic conversion system

Claim 2

Apparatus in a digital computation system for high-speed conversion of a floating point representation of a number into a logarithmic representation of said number, said floating point representation having a fractional portion and a floating point characteristic and said logarithmic representation having a mantissa portion and a log characteristic, said apparatus comprising: first means responsive to said fractional portion for providing an additive correction thereto having a value substantially equal to the difference between the normalized fractional portion of the corresponding number and said mantissa portion; and second means for combining said additive correction with said normalized fractional portion so as to produce said mantissa portion.

Claim 3

The apparatus of claim 1, wherein said first means includes normalization means for normalizing said fractional portion to said floating point representation; wherein said first means provides a predetermined additive correction having a value substantially equal to the difference between the normalized fractional portion and said mantissa portion.

Claim 4

The apparatus of claim 2 wherein said fractional portion is normalized to lie in the range of 1 to 2, whereby said additive corrections lie in the range of 0 to less than 1.

Claim 5

The apparatus of claim 2 wherein said first means comprises a memory storing predetermined additive corrections.

Claim 6

The apparatus of claim 4 wherein said normalized fractional portion defines an address in said memory for the corresponding correction.

Claim 7

The apparatus of claim 4 wherein said fractional portion is normalized to lie in the range of 0 to 1, wherein said first means includes: means for calculating from said fractional portion the address in said memory of the corresponding additive correction.

Claim 8

Apparatus in a digital computation system for high-speed conversion of a logarithmic representation of a number into a floating point representation, said logarithmic representation having a mantissa portion and a log characteristic and said floating point representation having a fractional portion and a floating point characteristic, said apparatus comprising: first means responsive to said mantissa portion for providing an additive correction thereto having a value substantially equal to the difference between the fractional portion of the corresponding number and said mantissa portion; and second means for combining said additive correction with said mantissa portion so as to produce said fractional portion.

Claim 9

Apparatus in a digital computation system for high-speed conversion of a logarithmic representation of a number into a floating point representation, said logarithmic representation having a mantissa portion and a log characteristic and said floating point representation having a fractional portion and a floating point characteristic, said apparatus comprising: first means responsive to said mantissa portion for providing an additive correction thereto having a value substantially equal to the difference between the fractional portion of the corresponding number and said mantissa portion; and second means for combining said additive correction with said mantissa portion so as to produce said fractional portion.

Claim 10

The apparatus of claim 7 wherein said first means comprises a memory storing predetermined additive corrections.

Claim 11

The apparatus of claim 8 wherein said second means further comprises: first adding means for forming the sum of said mantissa portion and the corresponding additive correction; and second adding means responsive to said sum for adding a factor of 1 thereto so as to produce a fractional portion of said floating point representation.

Claim 12

In a system employing logarithmic and floating point representations of numbers, said logarithmic representation having a mantissa portion and a log characteristic and said floating point representation having a fractional portion and a floating point characteristic, apparatus for converting back and forth between the mantissa and fractional portions of said representations at high speeds comprising: memory means for storing a plurality of additive correction values representing the differences between mantissa and fractional portions corresponding to the same numbers; and means operable to retrieve said correction values from said memory means and to selectively combine each such retrieved correction value with each of the mantissa portion and fractional portion corresponding thereto so as to selectively convert each portion into the corresponding counterpart portion.

Claim 13

In a system employing logarithmic and floating point representations of numbers, said logarithmic representation having a mantissa portion and a log characteristic and said floating point representation having a fractional portion and a floating point characteristic, apparatus for converting back and forth between the mantissa and fractional portions of said representations at high speeds comprising: memory means for storing a plurality of additive correction values representing the differences between mantissa and fractional portions corresponding to the same numbers; and means operable to retrieve said correction values from said memory means and to selectively combine each such retrieved correction value with each of the mantissa portion and fractional portion corresponding thereto so as to selectively convert each portion into the corresponding counterpart portion.

Claim 14

The apparatus of claim 10 wherein each said mantissa and fractional portions defines an address in said memory for the additive correction corresponding thereto.