US4583119A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Signal interface circuit
Assignee: US Philips Corp
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Filing: 1984-03-09
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Granted: 1986-04-15
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Expires: 2004-03-09
Abstract
Abstract A synchronizing signal interface circuit for a television monitor comprises two exclusive-NOR gates G1 and G2 which function as controllable inverters. Line and field sync. signals applied at respective input terminals T1 and T2 are fed to signal inputs SGN1 and SGN2 of the gates G1 and G2, and integrated versions of these signals are produced by respective integrators (Rb,Rc,C) and fed to control inputs INV1 and INV2. Each of the line and field sync. signals has a duty cycle which results in the logic level (0 or 1) of the sync. pulses of the signal being opposite to the logic level (1 or 0) of the integrated version. Due to the exclusive-NOR function of the gates G1 and G2, the logic level or polarity of the output sync. signal pulses will always be the same (negative), for both negative and positive polarity of the input sync. signal pulses. A gate G3 combines the output sync. signal pulses to produce a composite sync. signal.
Inventors
- 👤 John A. Roscoe
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 21:16
CPC Classifications
H; H04; H04N; H04N5/00; H04N5/04; H03; H03K; H03K5/00; H03K5/156
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
193 words
A signal interface circuit for receiving synchronizing signals for a television monitor, characterized in that said signal interface circuit comprises a controllable inverter having a signal input connected to receive a synchronizing signal comprising pulses having one of two possible logic levels, the signal having a duty cycle and assuming the other logic level between successive pulses, the inverter also having a output from which a restituted synchronizing signal is produced and a control input connected to receive an integrated version of said synchronizing signal, the interface circuit including an integrator having a time constant and which is connected to receive said synchronizing signal and is operable to produce said integrated version thereof, the time constant of the integrator in relation to the duty cycle of said synchronizing signal between the two logic levels being such that whichever one of the two logic levels the synchronizing pulses have, the integrated version of the synchronizing signal has the other logic level, the inverter effecting inversion of the signal at its input in response to one logic level of the integrated version at the control input, but not in response to the other logic level.
Claim 2
Dependent Claim
193 words
A signal interface circuit for receiving synchronizing signals for a television monitor, characterized in that said signal interface circuit comprises a controllable inverter having a signal input connected to receive a synchronizing signal comprising pulses having one of two possible logic levels, the signal having a duty cycle and assuming the other logic level between successive pulses, the inverter also having a output from which a restituted synchronizing signal is produced and a control input connected to receive an integrated version of said synchronizing signal, the interface circuit including an integrator having a time constant and which is connected to receive said synchronizing signal and is operable to produce said integrated version thereof, the time constant of the integrator in relation to the duty cycle of said synchronizing signal between the two logic levels being such that whichever one of the two logic levels the synchronizing pulses have, the integrated version of the synchronizing signal has the other logic level, the inverter effecting inversion of the signal at its input in response to one logic level of the integrated version at the control input, but not in response to the other logic level.
Claim 3
Dependent Claim
54 words
A signal interface circuit as claimed in claim 1, characterized in that the controllable inverter is an exclusive NOR-gate, the signal interface circuit being operable to provide said restituted synchronizing signal having pulses of negative sense or polarity in response to a synchronizing signal having pulses of either positive or negative sense or polarity.
Claim 4
Dependent Claim
121 words
A signal interface circuit as claimed in claim 1, for interfacing in respect of line and field television synchronizing signals which are to be received separately, characterized in that said signal interface circuit comprises a further controllable inverter and a further integrator which are organized and operable as said inverter and integrator, said integrator and inverter and said further integrator said said further inverter being connected to receive, respectively, said line and field television synchronizing signals, said signal interface circuit further comprising a combining gate having respective inputs to which restituted line and field synchronizing signals from the inverter and the further inverter, respectively, are applied, this combining gate providing at its output a restituted composite line and field synchronizing signal.
Claim 5
Dependent Claim
19 words
A signal interface circuit as claimed in claim 3, characterized in that said combining gate is an exclusive-NOR gate.
Claim 6
Dependent Claim
120 words
A signal interface circuit as claimed in claim 2, for interfacing in respect of line and field television synchronizing signals which are to be received separately, characterized in that said signal interface circuit comprises a further controllable inverter and a further integrator which are organized and operable as said inverter and integrator, said inverter and integrator and said further inverter and further integrator being connected to receive, respectively, said line and field television synchronizing signals, said signal interface circuit further comprising a combining gate having respective inputs to which restituted line and field synchronizing signals from the inverter and the further inverter, respectively, are applied, this combining gate providing at its output a restituted composite line and field synchronizing signal.
Claim 7
Dependent Claim
19 words
A signal interface circuit as claimed in claim 5, characterized in that said combining gate is an exclusive-NOR gate.
References Cited (Backward Citations)
JPS574619A
Cited
US4453183A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-04-14 | 1989-10-14 | 1990-04-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-04-14 | 1993-10-14 | 1994-04-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-04-14 | 1997-10-14 | 1998-04-15 | $7700.00 | Window Closed / Lapsed |