Signal delaying device

Claim 1

A signal delaying device comprising: a plurality of input terminals respectively receiving analog input signals of respective channels; a plurality of A-D converting means connected respectively to said respective input terminals and converting the input signals applied to said input terminals to digital signals; a multiplexer receiving output signals of said plurality of A-D converting means and outputting serial data of a single channel; memory means for sequentially storing the output signal data of said multiplexer and having plural addresses that are accessed in circulating order at a certain rate, the output signal data of said multiplexer being sequentially written at a predetermined period into the address then being accessed and as each such writing is carried out data is read out from the address where a writing operation was done a predetermined period of time before the present writing is done; a demultiplexer demultiplexing serial data sequentially read out from the respective addresses of said memory means into signals of plural channels; a plurality of D-A converting means for converting the demultiplexed digital signals of the respective channels into analog signals; a plurality of output terminals connected to outputs of said D-A converting means from which the analog signals of the respective channels are derived as output signals; control means for effecting designation of addresses and writing and reading operations of said memory means; and mode designation means for setting the number of channels of input signals to be processed, said control means being set in response to setting of the number of channels in such a manner that the address space of said memory means will be divided in use according to the set number of channels of input signals.