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US4575844A Expired / Lapsed US ⏱️ 0.0 years remaining

Digital switching system

Assignee: NTT Inc
•
Filing: 1984-05-30
•
Granted: 1986-03-11
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Expires: 2004-05-30
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Abstract

Abstract A hierarchical message channel storage of a digital switching system which is connected to time division multiplex transmission lines includes at least a small-capacity high-speed memory and a large-capacity low-speed memory. A control section performs switching using the high-speed memory when a circuit switching call is received. However, when a packet switching call is received, the control section accesses the high-speed memory to temporarily store transmission data in the high-speed memory and performs switching for one of the output transmission lines or the control section accesses the high- and low-speed memories to temporarily store data in the low-speed memory through said high-speed memory so as to perform switching for one of said output transmission lines. In this case, the access cycles of the high-speed memory have circuit/packet switching call cycles and switching program cycles. A single storage is commonly used for the circuit switching call requiring writing data at a high speed, the packet switching call requiring storing a great amount of data, and the switching program.

Inventors

  • 👤 Yasuharu Kosuge
  • 👤 Noriharu Miyaho

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-25 10:35
CPC Classifications
H; H04; H04L; H04L12/00; H04L12/64

Claims Analysis

Total Claims: 11
Claim 1
Independent Claim 164 words
A digital switching system comprising: a hierarchical storage connected to a plurality of input and output transmission lines serving as time division multiplex transmission lines, and a control section for controlling an operation of said hierarchical storage, said hierarchical storage including at least a small-capacity high-speed memory and a large-capacity low-speed memory, said control section being arranged such that said high-speed memory is accessed to immediately perform switching for one of said output transmission lines when states of said input transmission lines indicate a circuit switching call, and that said high-speed memory is accessed to temporarily store data in said high-speed memory and the stored data in the high-speed memory is sent out to one of said output transmission lines, or said high- and low-speed memories are accessed to store data in said low-speed memory through said high-speed memory so as to perform switching for one of said output transmission lines when the states of said input transmission lines indicate a packet switching call.
Claim 2
Dependent Claim 164 words
A digital switching system comprising: a hierarchical storage connected to a plurality of input and output transmission lines serving as time division multiplex transmission lines, and a control section for controlling an operation of said hierarchical storage, said hierarchical storage including at least a small-capacity high-speed memory and a large-capacity low-speed memory, said control section being arranged such that said high-speed memory is accessed to immediately perform switching for one of said output transmission lines when states of said input transmission lines indicate a circuit switching call, and that said high-speed memory is accessed to temporarily store data in said high-speed memory and the stored data in the high-speed memory is sent out to one of said output transmission lines, or said high- and low-speed memories are accessed to store data in said low-speed memory through said high-speed memory so as to perform switching for one of said output transmission lines when the states of said input transmission lines indicate a packet switching call.
Claim 3
Dependent Claim 25 words
A system according to claim 1, wherein said hierarchical storage further comprises a file memory for storing packet switching data corresponding to packet switching calls.
Claim 4
Dependent Claim 25 words
A system according to claim 1, wherein said hierarchical storage is commonly used for a switching program together with the circuit and packet switching calls.
Claim 5
Dependent Claim 33 words
A system according to claim 1, wherein the signals of the circuit and packet switching calls are transmitted on said time division multiplex transmission lines in accordance with a common signalling control system.
Claim 6
Dependent Claim 45 words
A system according to claim 1, wherein said high-speed memory has access cycles which comprise circuit or packet switching call cycles, and a switching program cycle, a single memory being commonly used in the circuit and packet switching call cycles and the switching program cycle.
Claim 7
Dependent Claim 31 words
A system according to claim 1, wherein said control section receives through a signal transmission/reception circuit a control signal from a common time slot on said time division multiplex transmission lines.
Claim 8
Dependent Claim 28 words
A system according to claim 6, wherein the control signal has a format including service indicator data for discriminating the circuit switching call from the packet switching call.
Claim 9
Dependent Claim 41 words
A system according to claim 6, wherein said control section performs the program cycle in place of a write/read cycle with respect to said high-speed memory when data to be switched does not exist on said time division multiplex transmission lines.
Claim 10
Dependent Claim 30 words
A system according to claim 1, wherein said control section includes means for inhibiting access of an area of said high-speed memory which is assigned to the circuit switching calls.
Claim 11
Dependent Claim 29 words
A system according to claim 1, wherein said control section includes means for preventing interruption of a write/read operation of data transmitted through said time division multiplex transmission lines.

References Cited (Backward Citations)

US3732548A Cited
US3988545A Cited
US4413337A Cited
US4494231A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1989-03-10 1989-09-09 1990-03-11 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1993-03-10 1993-09-09 1994-03-11 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1997-03-10 1997-09-09 1998-03-11 $7700.00 Window Closed / Lapsed

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