US4575760A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Noise reduction circuit for a video signal
Assignee: Victor Company of Japan Ltd
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Filing: 1984-04-04
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Granted: 1986-03-11
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Expires: 2004-04-04
Abstract
Abstract A noise reduction circuit for a video signal, comprises a delay circuit for delaying an input video signal by a predetermined delay time which is m times one horizontal scanning period, where m is an integer including one, a first adding circuit for adding the input video signal and the delayed video signal, a subtracting circuit for performing a subtraction between the input video signal and the delayed video signal, a noise clipping circuit for eliminating a noise component which is multiplexed at a zero level of an output signal of the subtracting circuit, and for producing a signal having a waveform corresponsing to a correlation error which is introduced in an output signal of the first adding circuit due to the addition performed in the first adding circuit, and a second adding circuit for adding the output signals of the first adding circuit and the noise clipping circuit so as to produce a video signal in which the correlation error has been compensated and the noise has been reduced.
Inventors
- 👤 Shintaro Nakagaki
- 👤 Ichiro Negishi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 08:30
CPC Classifications
H; H04; H04N; H04N5/00; H04N5/14; H04N5/21
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
296 words
A noise reduction circuit for a video signal, said noise reduction circuit comprising: a delay circuit supplied with an input video signal in which a noise has been multiplexed, for delaying said input video signal by a predetermined delay time which is m times one horizontal scanning period, where m is an integer including one; a first adding circuit supplied with said input video signal and an output delayed video signal of said delay circuit, for adding said input video signal and said delayed video signal; a subtracting circuit supplied with said input video signal and said output delayed video signal of said delay circuit, for performing a subtraction between said input video signal and said delayed video signal; a noise clipping circuit for eliminating a noise component which is multiplexed at a zero level of an output signal of said subtracting circuit, and for producing a signal having a waveform corresponding to a correlation error which is introduced in an output signal of said first adding circuit due to the addition performed in said first adding circuit; a second adding circuit supplied with the output signal of said first adding circuit and an output signal of said noise clipping circuit, for adding the output signals of said first adding circuit and said noise clipping circuit so as to produce a video signal in which the correlation error has been compensated and the noise has been reduced; and coefficient multiplying and adding circuit means for multiplying a predetermined coefficient βand the output video signal of said second adding circuit and for adding the multiplied signal to said input video signal, said delay circuit, said first adding circuit, and said subtracting circuit being respectively supplied with an output signal of said coefficient multiplying and adding circuit means.
Claim 2
Dependent Claim
296 words
A noise reduction circuit for a video signal, said noise reduction circuit comprising: a delay circuit supplied with an input video signal in which a noise has been multiplexed, for delaying said input video signal by a predetermined delay time which is m times one horizontal scanning period, where m is an integer including one; a first adding circuit supplied with said input video signal and an output delayed video signal of said delay circuit, for adding said input video signal and said delayed video signal; a subtracting circuit supplied with said input video signal and said output delayed video signal of said delay circuit, for performing a subtraction between said input video signal and said delayed video signal; a noise clipping circuit for eliminating a noise component which is multiplexed at a zero level of an output signal of said subtracting circuit, and for producing a signal having a waveform corresponding to a correlation error which is introduced in an output signal of said first adding circuit due to the addition performed in said first adding circuit; a second adding circuit supplied with the output signal of said first adding circuit and an output signal of said noise clipping circuit, for adding the output signals of said first adding circuit and said noise clipping circuit so as to produce a video signal in which the correlation error has been compensated and the noise has been reduced; and coefficient multiplying and adding circuit means for multiplying a predetermined coefficient βand the output video signal of said second adding circuit and for adding the multiplied signal to said input video signal, said delay circuit, said first adding circuit, and said subtracting circuit being respectively supplied with an output signal of said coefficient multiplying and adding circuit means.
Claim 3
Dependent Claim
35 words
A noise reduction circuit as claimed in claim 1 in which the noise level in the output video signal of said second adding circuit, is 1/√2 times the noise level in said input video signal.
Claim 4
Dependent Claim
55 words
A noise reduction circuit as claimed in claim 1 in which said coefficient multiplying and adding circuit means comprises a multiplier for multiplying said predetermined coefficient β to the output video signal of said second adding circuit, and a third adding circuit for adding an output signal of said multiplier and said input video signal.
Claim 5
Dependent Claim
112 words
A noise reduction circuit as claimed in claim 1 in which said coefficient multiplying and adding circuit means comprises a coefficient multiplying and adding circuit which is made up of a first resistor of a resistance R 1 supplied with said input video signal, and a second resistor of a resistance R 2 supplied with the output signal of said second adding circuit, said first and second resistors are commonly coupled at an adding point, and said output video signal of said second adding circuit is multiplied by said coefficient β satisfying an equation β=R 1 /(R 1 +R 2 ) and added with said input video signal at said adding point.
Claim 6
Dependent Claim
33 words
A noise reduction circuit as claimed in claim 1 in which said second adding circuit produces a video signal which has been reduced of the noise by a noise improvement described by ##EQU4##
Claim 7
Dependent Claim
75 words
A noise reduction circuit as claimed in claim 1 in which said subtracting circuit comprises a differential amplifier which includes a pair of transistors, said noise clipping circuit comprises a circuit which includes a pair of diodes coupled in parallel with mutually opposite polarities, and one of said pair of transistors coupled to said pair of diodes also acts to compensate for a non-linear operating characteristic of a circuit which includes said pair of diodes.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-03-10 | 1989-09-09 | 1990-03-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-03-10 | 1993-09-09 | 1994-03-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-03-10 | 1997-09-09 | 1998-03-11 | $7700.00 | Window Closed / Lapsed |