Circuit for establishing accurate sample timing

Claim 2

A circuit for establishing accurate sample timing by correcting sampling frequency offsets and sampling phase offsets, said circuit forming part of a demodulator for an orthogonally multiplexed parallel data transmission system, said demodulator including a demodulating section which receives the orthogonally multiplexed parallel data to recover baseband signals of corresponding parallel channels which consist of data and pilot channels, said circuit comprising: a first second-order PLL which includes a first integrator, said first second-order PLL being arranged after said demodulating section so as to receive a recovered baseband signal of a first pilot channel; a second second-order PLL which includes a second integrator, said second second-order PLL being arranged after said demodulating section so as to receive a recovered baseband signal of a second pilot channel; a subtracter which is supplied with the outputs of said first and second integrators and which produces the subtraction result as sampling frequency offset information; and a voltage-controlled oscillator which receives the output of said subtracter so as to establish the accurate sample timing.

Claim 3

A circuit as claimed in claim 1, wherein said first and second pilot channels are the end channels of said parallel channels.

Claim 4

A circuit as claimed in claim 1, further including; a plurality of automatic equalizers which are allotted to the data channels inclusive of the center channel of said parallel channels, said plurality of automatic equalizers producing sampling phase offset information; and an adder which adds said sampling frequency offset information and said sampling phase offset information, said adder applying the output thereof to said voltage-controlled oscillator.

Claim 5

A circuit as claimed in claim 3, wherein said first and second pilot channels are the end channels of said parallel channels.

Claim 6

A circuit for establishing accurate sample timing by correcting sampling frequency offsets and sampling phase offsets, said circuit forming part of a demodulator for an orthogonally multiplexed parallel data transmission system, said demodulator including a demodulating section which receives the orthogonally multiplexed parallel data to recover baseband signals of corresponding parallel channels which consist of data and pilot channels, said circuit comprising: a first second-order PLL which includes a first integrator, said first second-order PLL being arranged after said demodulating section so as to receive a recovered baseband signal of a first pilot channel; a second second-order PLL which includes a second integrator, said second second-order PLL being arranged after said demodulating section so as to receive a recovered baseband signal of a second pilot channel; a subtracter which is supplied with the outputs of said first and second integrators and which produces the subtraction result as sampling frequency offset information; a plurality of automatic equalizers which are allotted to the data channels inclusive of the center channel of said parallel channels, said plurality of automatic equalizers producing sampling phase offset information; an adder which adds said sampling frequency offset information and said sampling phase offset information; and a voltage-controlled oscillator which receives the output of said adder so as to establish the accurate sample timing.

Claim 7

A circuit for establishing accurate sample timing by correcting sampling frequency offsets and sampling phase offsets, said circuit forming part of a demodulator for an orthogonally multiplexed parallel data transmission system, said demodulator including a demodulating section which receives the orthogonally multiplexed parallel data to recover baseband signals of corresponding parallel channels which consist of data and pilot channels, said circuit comprising: a first second-order PLL which includes a first integrator, said first second-order PLL being arranged after said demodulating section so as to receive a recovered baseband signal of a first pilot channel; a second second-order PLL which includes a second integrator, said second second-order PLL being arranged after said demodulating section so as to receive a recovered baseband signal of a second pilot channel; a subtracter which is supplied with the outputs of said first and second integrators and which produces the subtraction result as sampling frequency offset information; a plurality of automatic equalizers which are allotted to the data channels inclusive of the center channel of said parallel channels, said plurality of automatic equalizers producing sampling phase offset information; an adder which adds said sampling frequency offset information and said sampling phase offset information; and a voltage-controlled oscillator which receives the output of said adder so as to establish the accurate sample timing.

Claim 8

A circuit as claimed in claim 5, wherein said first and second pilot channels are the end channels of said parallel channels.

Claim 9

A circuit for establishing accurate sample timing by correcting sampling frequency offsets and sampling phase offsets, said circuit forming part of a demodulator for an orthogonally multiplexed parallel data transmission system, said demodulator including a demodulating section which receives the orthogonally multiplexed parallel data to recover baseband signals of corresponding parallel channels which consist of data and pilot channels, said circuit comprising: a first second-order PLL which includes a first integrator, said first second-order PLL being arranged after said demodulating section so as to receive a recovered baseband signal of a first pilot channel; a second second-order PLL which includes a second integrator, said second second-order PLL being arranged after said demodulating section so as to receive a recovered baseband signal of a second pilot channel; a subtracter which is supplied with the outputs of said first and second integrators and which produces the subtraction result as sampling frequency offset information; a plurality of automatic equalizers which are allotted to the data channels inclusive of the center channel of said parallel channels, said plurality of automatic equalizers producing sampling phase offset information; a voltage-controlled oscillator which is adapted to control the sample timing; a selector which allows said sampling frequency offset information to be applied to said voltage-controlled oscillator during a predetermined period after the system is initially operated, and which allows said sampling phase offset information to be applied to said voltage-controlled oscillator after said predetermined period elapses.

Claim 10

A circuit for establishing accurate sample timing by correcting sampling frequency offsets and sampling phase offsets, said circuit forming part of a demodulator for an orthogonally multiplexed parallel data transmission system, said demodulator including a demodulating section which receives the orthogonally multiplexed parallel data to recover baseband signals of corresponding parallel channels which consist of data and pilot channels, said circuit comprising: a first second-order PLL which includes a first integrator, said first second-order PLL being arranged after said demodulating section so as to receive a recovered baseband signal of a first pilot channel; a second second-order PLL which includes a second integrator, said second second-order PLL being arranged after said demodulating section so as to receive a recovered baseband signal of a second pilot channel; a subtracter which is supplied with the outputs of said first and second integrators and which produces the subtraction result as sampling frequency offset information; a plurality of automatic equalizers which are allotted to the data channels inclusive of the center channel of said parallel channels, said plurality of automatic equalizers producing sampling phase offset information; a voltage-controlled oscillator which is adapted to control the sample timing; a selector which allows said sampling frequency offset information to be applied to said voltage-controlled oscillator during a predetermined period after the system is initially operated, and which allows said sampling phase offset information to be applied to said voltage-controlled oscillator after said predetermined period elapses.

Claim 11

A circuit as claimed in claim 7, wherein said first and second pilot channels are the end channels of said parallel channels.

Claim 12

A circuit for establishing accurate sample timing by correcting sampling frequency offsets and sampling phase offsets, said circuit forming part of a demodulator for an orthogonally multiplexed parallel data transmission system, said demodulator including a demodulating section which receives the orthogonally multiplexed parallel data to recover baseband signals of corresponding parallel channels which consist of data and pilot channels, said circuit comprising: a first second-order PLL which includes a first integrator, said first second-order PLL being arranged after said demodulating section so as to receive a recovered baseband signal of a first pilot channel; a second second-order PLL which includes a second integrator, said second second-order PLL being arranged after said demodulating section so as to receive a recovered baseband signal of a second pilot channel; a subtracter which is supplied with the outputs of said first and second integrators and which produces the subtraction result as sampling frequency offset information; a plurality of automatic equalizers which are allotted to the data channels inclusive of the center channel of said parallel channels, said plurality of automatic equalizers producing sampling phase offset information; a voltage-controlled oscillator which is adapted to control the sample timing; a detector for detecting the absolute value of said sampling frequency offset; and a selector which allows said sampling frequency offset information to be applied to said voltage-controlled oscillator when said detector detects the absolute value in excess of a predetermined value, and which allows said sampling phase offset information to be applied to said voltage-controlled oscillator when the absolute value detected by said detector is less than the predetermined value.

Claim 13

A circuit for establishing accurate sample timing by correcting sampling frequency offsets and sampling phase offsets, said circuit forming part of a demodulator for an orthogonally multiplexed parallel data transmission system, said demodulator including a demodulating section which receives the orthogonally multiplexed parallel data to recover baseband signals of corresponding parallel channels which consist of data and pilot channels, said circuit comprising: a first second-order PLL which includes a first integrator, said first second-order PLL being arranged after said demodulating section so as to receive a recovered baseband signal of a first pilot channel; a second second-order PLL which includes a second integrator, said second second-order PLL being arranged after said demodulating section so as to receive a recovered baseband signal of a second pilot channel; a subtracter which is supplied with the outputs of said first and second integrators and which produces the subtraction result as sampling frequency offset information; a plurality of automatic equalizers which are allotted to the data channels inclusive of the center channel of said parallel channels, said plurality of automatic equalizers producing sampling phase offset information; a voltage-controlled oscillator which is adapted to control the sample timing; a detector for detecting the absolute value of said sampling frequency offset; and a selector which allows said sampling frequency offset information to be applied to said voltage-controlled oscillator when said detector detects the absolute value in excess of a predetermined value, and which allows said sampling phase offset information to be applied to said voltage-controlled oscillator when the absolute value detected by said detector is less than the predetermined value.

Claim 14

A circuit as claimed in claim 9, wherein said first and second pilot channels are the end channels of said parallel channels.