US4574365A
Expired / Lapsed
US
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Shared access lines memory cells
Assignee: International Business Machines Corp
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Filing: 1983-04-18
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Granted: 1986-03-04
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Expires: 2003-04-18
Abstract
Abstract A memory array is provided which includes a common sense line to which is connected a first storage capacitor through first switching means and a second storage capacitor through second switching means, with a common word line connected to the control electrodes of the first and second switching means, a first bit line connected to a plate of the first storage capacitor and a second bit line connected to a plate of the second storage capacitor. Data is stored into or read from the first storage capacitor by selecting the common word line and the first bit line and data is stored into and read from the second storage capacitor by selecting the common word line and the second bit line, with the data from both storage capacitors being detected on the common sense line.
Inventors
- 👤 Roy E. Scheuerlein
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 19:58
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; G11C11/409; G11C11/4097
Claims Analysis
Total Claims: 31
Claim 1
Independent Claim
91 words
In a read/write memory array including at least first and second data storage cells for independently storing data signals, each data storage cell having a control electrode-responsive switching device for serially connecting a storage capacitance between a data sense node and a reference node, the improvement characterized in that the respective control electrodes of the first and second data storage cells are electrically connected to a first common line and the respective data sense nodes of the first and second data storage cells are electrically connected to a second common line.
Claim 2
Dependent Claim
91 words
In a read/write memory array including at least first and second data storage cells for independently storing data signals, each data storage cell having a control electrode-responsive switching device for serially connecting a storage capacitance between a data sense node and a reference node, the improvement characterized in that the respective control electrodes of the first and second data storage cells are electrically connected to a first common line and the respective data sense nodes of the first and second data storage cells are electrically connected to a second common line.
Claim 3
Dependent Claim
71 words
A memory comprising first and second data storage cells each having a data sense node and a reference node, a common sense line connected to each of said data sense nodes, and first and second means for producing data signals, said first means being connected to the reference node of said first data storage cell and said second means being connected to the reference node of said second data storage cell.
Claim 4
Dependent Claim
71 words
A memory comprising first and second data storage cells each having a data sense node and a reference node, a common sense line connected to each of said data sense nodes, and first and second means for producing data signals, said first means being connected to the reference node of said first data storage cell and said second means being connected to the reference node of said second data storage cell.
Claim 5
Dependent Claim
29 words
A memory as set forth in claim 2 wherein each of said cells includes switching means having a control electrode and a storage capacitor connected to said switching means.
Claim 6
Dependent Claim
17 words
A memory as set forth in claim 3 further including means for simultaneously operating said switching means.
Claim 7
Dependent Claim
30 words
A memory as set forth in claim 3 wherein said switching means in each of said cells is disposed between said sense line and said capacitor of the respective cell.
Claim 8
Dependent Claim
38 words
A memory as set forth in claim 5 wherein each of said cells further includes a second capacitor connected serially with said storage capacitor between said reference node of the respective cell and a point of reference potential.
Claim 9
Dependent Claim
27 words
A memory as set forth in claim 4 wherein said operating means includes a word line connected to the control electrode of each of said switching means.
Claim 10
Dependent Claim
19 words
A memory as set forth in claim 7 wherein each of said switching means includes a field effect transistor.
Claim 11
Dependent Claim
54 words
A memory as set forth in claim 2 further including a sense amplifier arranged to produce a first data voltage on a first node and a second data voltage on a second node, said first node being coupled to said sense line and said second node being coupled to each of said reference nodes.
Claim 12
Dependent Claim
58 words
A memory as set forth in claim 9 further including first and second write back switching means, said first write back switching means being interposed between said second node and said reference node of said first cell and said second write back switching means being interposed between said second node and said reference node of said second cell.
Claim 13
Dependent Claim
19 words
A memory as set forth in claim 10 further including means for selectively grounding each of said reference nodes.
Claim 14
Dependent Claim
85 words
A memory system comprising a common sense line, first and second bit lines, a first storage cell connected between said sense line and said first bit line, a second storage cell connected between said sense line and said second bit line, first switching means, a sense amplifier having a first node connected to said sense line and a second node connected to said first and second bit lines through said switching means, and means for applying data signals to said first and second bit lines.
Claim 15
Dependent Claim
85 words
A memory system comprising a common sense line, first and second bit lines, a first storage cell connected between said sense line and said first bit line, a second storage cell connected between said sense line and said second bit line, first switching means, a sense amplifier having a first node connected to said sense line and a second node connected to said first and second bit lines through said switching means, and means for applying data signals to said first and second bit lines.
Claim 16
Dependent Claim
36 words
A memory system as set forth in claim 12 wherein each of said first and second cells includes a storage capacitor and second switching means and further including means for simultaneously operating said second switching means.
Claim 17
Dependent Claim
34 words
A memory system as set forth in claim 13 wherein each of said second switching means includes a field effect transistor interposed between said sense line and said storage capacitor of the respective cell.
Claim 18
Dependent Claim
27 words
A memory system as set forth in claim 14 wherein said operating means includes a word line connected to the control gate of each of said transistors.
Claim 19
Dependent Claim
69 words
A memory system as set forth in claim 15 wherein said first cell further includes a second capacitor serially connected with said storage capacitor of said first cell between said first bit line and a point of reference potential and said second cell further includes a second capacitor serially connected with said storage capacitor of said second cell between said second bit line and said point of reference potential.
Claim 20
Dependent Claim
158 words
A memory system comprising a sense line, first and second bit lines, a first storage cell storing a first signal voltage therein connected between said sense line and said first bit line, a second storage cell storing a second signal voltage therein connected between said sense line and said second bit line, means coupled to said sense line for producing a first true signal of said first signal voltage and a first complementary signal representative of said first signal voltage, means for applying said first complementary signal to said first bit line, means for producing a second true signal of said second signal voltage and a second complementary signal representative of said second signal voltage, means for applying said second complementary signal to said second bit line, and means coupled to said sense line and to said first and second bit lines for restoring said first and second signal voltages to said first and second storage cells, respectively.
Claim 21
Dependent Claim
158 words
A memory system comprising a sense line, first and second bit lines, a first storage cell storing a first signal voltage therein connected between said sense line and said first bit line, a second storage cell storing a second signal voltage therein connected between said sense line and said second bit line, means coupled to said sense line for producing a first true signal of said first signal voltage and a first complementary signal representative of said first signal voltage, means for applying said first complementary signal to said first bit line, means for producing a second true signal of said second signal voltage and a second complementary signal representative of said second signal voltage, means for applying said second complementary signal to said second bit line, and means coupled to said sense line and to said first and second bit lines for restoring said first and second signal voltages to said first and second storage cells, respectively.
Claim 22
Dependent Claim
42 words
A memory system as set forth in claim 17 wherein each of said storage cells includes a field effect transistor serially connected with a storage capacitor forming a storage node at the common point therebetween at which said signal voltages are stored.
Claim 23
Dependent Claim
48 words
A memory system as set forth in claim 18 wherein in each of said cells said storage capacitor is connected to said sense line through said transistor and each of said cells further includes a second capacitor connected between said storage node and a point of reference potential.
Claim 24
Dependent Claim
148 words
A memory comprising a sense line, first and second bit lines, first switching means having a control electrode interposed between said sense line and said first bit line, a first storage capacitor having a first conductive plate connected to said first bit line and a second conductive plate connected to said sense line through said first switching means, second switching means having a control electrode interposed between said sense line and said second bit line, a second storage capacitor having a first conductive plate connected to said second bit line and a second conductive plate connected to said sense line through said second switching means, a word line connected to said control electrodes, means for selectively applying a voltage pulse to said word line, means for selectively applying a voltage to said sense line, and means for selectively applying data signals to said first and second bit lines.
Claim 25
Dependent Claim
148 words
A memory comprising a sense line, first and second bit lines, first switching means having a control electrode interposed between said sense line and said first bit line, a first storage capacitor having a first conductive plate connected to said first bit line and a second conductive plate connected to said sense line through said first switching means, second switching means having a control electrode interposed between said sense line and said second bit line, a second storage capacitor having a first conductive plate connected to said second bit line and a second conductive plate connected to said sense line through said second switching means, a word line connected to said control electrodes, means for selectively applying a voltage pulse to said word line, means for selectively applying a voltage to said sense line, and means for selectively applying data signals to said first and second bit lines.
Claim 26
Dependent Claim
22 words
A memory system as set forth in claim 20 wherein said first and second switching means each includes a field effect transistor.
Claim 27
Dependent Claim
25 words
A memory system as set forth in claim 21 further including means coupled to said sense line for detecting voltage changes in said sense line.
Claim 28
Dependent Claim
26 words
A memory system as set forth in claim 22 wherein said voltage change detecting means includes a differential sense amplifier having first and second sense nodes.
Claim 29
Dependent Claim
50 words
A memory system as set forth in claim 23 further including third and fourth switching means and wherein said sense line is connected to said first sense node and said first and second bit lines are connected through said third and fourth switching means, respectively, to said second sense node.
Claim 30
Dependent Claim
32 words
A memory system as set forth in claim 24 wherein said means for selectively applying data signals includes means for selectively connecting said first and second bit lines to a reference potential.
Claim 31
Dependent Claim
54 words
A memory system as set forth in claim 20 further including a third storage capacitor connected between said second conductive plate of said first storage capacitor and a point of reference potential, and a fourth storage capacitor connected between said second conductive plate of said second storage capacitor and said point of reference potential.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-03-03 | 1989-09-02 | 1990-03-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-03-03 | 1993-09-02 | 1994-03-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-03-03 | 1997-09-02 | 1998-03-04 | $7700.00 | Window Closed / Lapsed |