US4573143A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor memory device having tunnel diodes
Assignee: Toshiba Corp
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Filing: 1983-03-07
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Granted: 1986-02-25
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Expires: 2003-03-07
Abstract
Abstract A semiconductor memory device has at least one memory cell which includes first and second tunnel diodes connected in series in a forward-bias direction between first and second power source terminals. The first and second power source terminals are held at constant potentials. A switching MOS transistor is connected at one end to a connection point between the first and second tunnel diodes. The potential at the connection point between the first and second tunnel diodes is determined by the potential at the other end of the switching MOS transistor.
Inventors
- 👤 Naohiro Matsukawa
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 17:27
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/36; G11C11/38
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
131 words
A semiconductor memory device comprising: at least one memory cell having first and second power source terminals held at substantially constant potentials, first and second tunnel diodes connected in series in a forward-bias direction between the first and second power source terminals and a switching means connected at one end to a connection point between the first and second tunnel diodes; a bit line connected to the other end of said switching means; and a word line connected to said switching means to supply a signal for controlling the conduction state of said switching means, the potential at the connection point between said first and second tunnel diodes being set at one of predetermined first and second potential levels during a write operation according to the potential on said bit line.
Claim 2
Dependent Claim
131 words
A semiconductor memory device comprising: at least one memory cell having first and second power source terminals held at substantially constant potentials, first and second tunnel diodes connected in series in a forward-bias direction between the first and second power source terminals and a switching means connected at one end to a connection point between the first and second tunnel diodes; a bit line connected to the other end of said switching means; and a word line connected to said switching means to supply a signal for controlling the conduction state of said switching means, the potential at the connection point between said first and second tunnel diodes being set at one of predetermined first and second potential levels during a write operation according to the potential on said bit line.
Claim 3
Dependent Claim
34 words
A semiconductor memory device according to claim 1, further comprising at least one dummy cell which has two tunnel diodes and a switching means connected to a connection point between the two tunnel diodes.
Claim 4
Dependent Claim
34 words
A semiconductor memory device according to claim 2, wherein the connection point between said two tunnel diodes of said dummy cell is set at a potential level between the first and second potential levels.
Claim 5
Dependent Claim
16 words
A semiconductor memory device according to claim 2, wherein said switching means is a MOS transistor.
Claim 6
Dependent Claim
16 words
A semiconductor memory device according to claim 1, wherein said switching means is a MOS transistor.
Claim 7
Dependent Claim
85 words
A memory cell comprising: first and second power source terminals held at substantially constant potentials; first and second tunnel diodes connected in series in a forward-bias direction between said first and second power source terminals; and a switching means connected at one end to a connection point between said first and second tunnel diodes, the potential at the connection point being set at approximately one of the first and second predetermined potential levels according to the potential at the other end of said switching means.
Claim 8
Dependent Claim
85 words
A memory cell comprising: first and second power source terminals held at substantially constant potentials; first and second tunnel diodes connected in series in a forward-bias direction between said first and second power source terminals; and a switching means connected at one end to a connection point between said first and second tunnel diodes, the potential at the connection point being set at approximately one of the first and second predetermined potential levels according to the potential at the other end of said switching means.
Claim 9
Dependent Claim
15 words
A memory cell according to claim 6, wherein said switching means is a MOS transistor.
References Cited (Backward Citations)
US3855582A
Cited
DE2425739A1
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-02-24 | 1989-08-26 | 1990-02-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-02-24 | 1993-08-26 | 1994-02-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-02-24 | 1997-08-26 | 1998-02-25 | $7700.00 | Window Closed / Lapsed |