US4572995A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Synchronism discriminating circuit
Assignee: Victor Company of Japan Ltd
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Filing: 1984-08-08
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Granted: 1986-02-25
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Expires: 2004-08-08
Abstract
Abstract A synchronism discriminating circuit comprises a phase comparator supplied with a reference signal having a reference frequency and a reference phase and with an input signal of which a synchronism with respect to the reference signal is to be discriminated, for comparing the phase of the reference signal with the phase of the input signal and for producing an output signal responsive to a phase difference between the two signals, where the reference signal is made up of a series of pulses, and a discriminating circuit supplied with the reference signal and with the output signal of the phase comparator, for counting the pulses in the reference signal during a period in which the phase difference is within a predetermined range and for producing a synchronism discrimation signal when a predetermined number or more pulses in the reference signal are continuously counted.
Inventors
- 👤 Ken Enami
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 11:14
CPC Classifications
H; H03; H03L; H03L7/00; H03L7/06; H03L7/08; H03L7/085; H03L7/095; G; G01; G01P; G01P3/00; G01P3/42; G01P3/56; G01P3/565; G01R; G01R25/00; G01R25/08; H02; H02P; H02P23/00; H02P23/18; H02P23/186; Y; Y10; Y10S; Y10S388/00; Y10S388/90; Y10S388/902; Y10S388/907; Y10S388/912
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
153 words
A synchronism discriminating circuit comprising: phase comparator means supplied with a reference signal having a reference frequency and a reference phase and with an input signal of which a synchronism with respect to said reference signal is to be discriminated, for comparing the phase of said reference signal with the phase of said input signal and for producing an output signal responsive to a phase difference between the two signals, said reference signal being made up of a series of pulses; and synchronization detecting circuit means supplied with said reference signal and with the output signal of said phase comparator means, for producing a sychronism detection signal, said synchronization detecting circuit means counting the pulses in said reference signal during a period in which said phase difference is within a predetermined range and producing said synchronism detection signal when at least a predetermined number of pulses in said reference signal are continuously counted.
Claim 2
Dependent Claim
153 words
A synchronism discriminating circuit comprising: phase comparator means supplied with a reference signal having a reference frequency and a reference phase and with an input signal of which a synchronism with respect to said reference signal is to be discriminated, for comparing the phase of said reference signal with the phase of said input signal and for producing an output signal responsive to a phase difference between the two signals, said reference signal being made up of a series of pulses; and synchronization detecting circuit means supplied with said reference signal and with the output signal of said phase comparator means, for producing a sychronism detection signal, said synchronization detecting circuit means counting the pulses in said reference signal during a period in which said phase difference is within a predetermined range and producing said synchronism detection signal when at least a predetermined number of pulses in said reference signal are continuously counted.
Claim 3
Dependent Claim
110 words
A synchronism discriminating circuit as claimed in claim 1 in which said discriminating means comprises a reference pulse width generating means supplied with said reference signal and triggered in response responsive to said reference signal, a first flip-flop having a data terminal supplied with the output signal of said phase comparator means and having a clock terminal supplied with an output signal of said reference pulse width generating means, and a binary counter having a clock terminal supplied with said reference signal and having a reset terminal supplied with an output signal of said first flip-flop, said binary counter producing said synchronism discrimination signal through a predetermined output terminal thereof.
Claim 4
Dependent Claim
39 words
A synchronism discriminating circuit as claimed in claim 2 in which said synchronization detecting circuit means further comprises a second flip-flop supplied with output signals of said binary counter and said first flip-flop, for producing said synchronism detection signal.
Claim 5
Dependent Claim
49 words
A synchronism discriminating circuit as claimed in claim 3 in which said synchronization dectecting circuit means further comprises an AND gate supplied with signals produced through a plurality of counter, for supplying an output output terminals of said binary counter, for supplying an output signal to said second flip-flop.
Claim 6
Dependent Claim
59 words
A synchronism discriminating circuit as claimed in claim 2 in which said synchronization detecting circuit means further comprises an inverter for inverting the phase of the output signal of said reference pulse width generating means and for supplying an output signal to said first flip-flop, said first flip-flop supplying a Q-output to the reset terminal of said binary counter.
Claim 7
Dependent Claim
21 words
A synchronism discriminating circuit as claimed in claim 2 in which said reference pulse width generating means comprises a monostable multivibrator.
Claim 8
Dependent Claim
21 words
A synchronism discriminating circuit as claimed in claim 3 in which said reference pulse width generating means comprises a monostable multivibrator.
Claim 9
Dependent Claim
21 words
A synchronism discriminating circuit as claimed in claim 4 in which said reference pulse width generating means comprises a monostable multivibrator.
Claim 10
Dependent Claim
21 words
A synchronism discriminating circuit as claimed in claim 5 in which said reference pulse width generating means comprises a monostable multivibrator.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-02-24 | 1989-08-26 | 1990-02-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-02-24 | 1993-08-26 | 1994-02-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-02-24 | 1997-08-26 | 1998-02-25 | $7700.00 | Window Closed / Lapsed |