US4571708A
Expired / Lapsed
US
⏱️ 0.0 years remaining
CMOS ROM Data select circuit
Assignee: STMicroelectronics lnc USA
•
Filing: 1984-12-26
•
Granted: 1986-02-18
•
Expires: 2004-12-26
Abstract
Abstract A data select circuit for selecting a column line in a CMOS ROM and for establishing a connection between a pair of bit lines and corresponding data lines uses a single NMOS pull-down transistor on the column line and a pair of P-channel pass transistors on the bit lines, the pass transistor gates being controlled not by an inverted column decode line, but by the column line itself, thus reducing the capacative load on the column decoder and saving space.
Inventors
- 👤 Harold L. Davis
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 19:34
CPC Classifications
G; G11; G11C; G11C17/00; G11C17/08; G11C17/10; G11C17/12; G11C17/126
Claims Analysis
Total Claims: 2
Claim 1
Independent Claim
187 words
A data selection circuit for a CMOS memory integrated circuit having a column line bracketed by first and second bit lines and having at least one pair of data storage transistors connected respectively between said column line and said first bit line and between said column line and said second bit line, each pair of said at least one pair of data storage transistors having a gate connected to a common row line of a set of at least one row line, said column line being connected through an N-channel pull-down transistor to ground and each of said bit lines being connected through a P-channel pass transistor to first and second data lines, respectively, in which said pull-down transistor has a gate electrode connected to a column decode line and each of said pass transistors has a gate connected to said column line, whereby a transition from a positive voltage to ground on said column line in response to a signal on said column decode line turns on said P-channel pass transistors, establishing a current path between each of said bit lines and a corresponding data line.
Claim 2
Dependent Claim
187 words
A data selection circuit for a CMOS memory integrated circuit having a column line bracketed by first and second bit lines and having at least one pair of data storage transistors connected respectively between said column line and said first bit line and between said column line and said second bit line, each pair of said at least one pair of data storage transistors having a gate connected to a common row line of a set of at least one row line, said column line being connected through an N-channel pull-down transistor to ground and each of said bit lines being connected through a P-channel pass transistor to first and second data lines, respectively, in which said pull-down transistor has a gate electrode connected to a column decode line and each of said pass transistors has a gate connected to said column line, whereby a transition from a positive voltage to ground on said column line in response to a signal on said column decode line turns on said P-channel pass transistors, establishing a current path between each of said bit lines and a corresponding data line.
References Cited (Backward Citations)
JPS56159897A
Cited
JPS5883392A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-02-17 | 1989-08-19 | 1990-02-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-02-17 | 1993-08-19 | 1994-02-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-02-17 | 1997-08-19 | 1998-02-18 | $7700.00 | Window Closed / Lapsed |