Input/output device for programmable controller

Claim 2

An input/output device for receiving external input signals and delivering external output signals for a programmable controller separately provided from said input/output device, comprising: two serial data input/output terminals, a clock signal input terminal, a shift register shifted by a clock signal applied to said clock signal input terminal, a clock circuit connected to a parallel output end of said shift register, a driver for sending out in parallel an output as external output signals from a latch circuit, a receiver for applying external input signals received, in parallel, to a parallel input end of said shift register, change-over means for switching depending upon which input end or output end is to be selected out of said two serial data input/output terminals in relation with said shift register, and a control circuit for stopping said clock signal in said clock signal conductor, for detecting the fixing of the signal level in said signal conductor for more than a predetermined period of time, and for producing a latch signal for said latch circuit, a parallel data read signal for said shift register and a control signal for said change-over means.

Claim 3

The input/output device for the programmable controller of claim 1, said shift register being a bidirectional register.

Claim 4

The input/output device for the programmable controller of claim 1, said shift register being a one-directional register.

Claim 5

An input/output device for a programmable controller, comprising; two serial data input/output terminals A and B, a clock signal input terminal, a (X+1)-bit shift register shifted only in one direction by a clock signal applied to said clock signal input terminal, a latch circuit connected to parallel output ends of 1 to X bits of said shift register, a driver for sending out in parallel an output from said latch circuit as external output signals, a receiver for receiving in parallel input signals and applying said input signals to parallel input ends of 1 to X bits of said shift register, a circuit for always applying a high level (H) signal to an input end of (X+1)th bit of said shift register, a change-over circuit to be switched to any one of the states where a signal applied to said input/output terminal A is used as a serial input of said shift register and a serial output obtained from an output end of X-th bit of said shift register is sent to said input/output terminal B, and where a signal applied to said input/output terminal B is a serial input of said shift register and a serial output obtained from an output end of (X+1)th bit of said shift register is sent to said input/output terminal A, and a control circuit for detecting the fixing of the level of a signal applied to said clock signal input terminal for more than a predetermined period of time and for producing a latch signal for said latch circuit, a parallel input read signal for said shift register and an inverted signal for said change over circuit.

Claim 6

An input/output device for a programmable controller, comprising; two serial data input/output terminals A and B, a clock signal input terminal, a (X+1)-bit shift register shifted only in one direction by a clock signal applied to said clock signal input terminal, a latch circuit connected to parallel output ends of 1 to X bits of said shift register, a driver for sending out in parallel an output from said latch circuit as external output signals, a receiver for receiving in parallel input signals and applying said input signals to parallel input ends of 1 to X bits of said shift register, a circuit for always applying a high level (H) signal to an input end of (X+1)th bit of said shift register, a change-over circuit to be switched to any one of the states where a signal applied to said input/output terminal A is used as a serial input of said shift register and a serial output obtained from an output end of X-th bit of said shift register is sent to said input/output terminal B, and where a signal applied to said input/output terminal B is a serial input of said shift register and a serial output obtained from an output end of (X+1)th bit of said shift register is sent to said input/output terminal A, and a control circuit for detecting the fixing of the level of a signal applied to said clock signal input terminal for more than a predetermined period of time and for producing a latch signal for said latch circuit, a parallel input read signal for said shift register and an inverted signal for said change over circuit.

Claim 7

The input/output device for the programmable controller of claim 4, said change-over circuit being formed with a driver with gates and logic gates.

Claim 8

An input/output device for a programmable controller, comprising: two serial data input terminals A and B, a shift register shifted by a clock signal applied to said clock signal input terminal, a latch circuit connected to a parallel output end of said shift register, a driver for sending out in parallel an output from said latch circuit as external output signals, a receiver for receiving in parallel external input signals and applying said external input signals to parallel input terminals of said shift register, a change-over circuit for switching to any one of the states where a signal applied to said input terminal A is a serial input of said shift register and a serial output of said shift register is sent to said input/output terminal B, and where a signal applied to said input/output terminal B is a serial input of said shift register and a serial output of said shift register is sent to said input/output terminal A, a control circuit for detecting the fixing of the level of a signal applied to said clock signal input terminal for more than a predetermined period of time T1 and for producing a latch signal for said latch circuit, a parallel input read signal for said shift register and an inverted signal for said change-over circuit, and a reset circuit for detecting the fixing of the level of a signal applied to said clock signal input terminal for a predetermined period of time sufficiently longer than said period of time T1 and for returning said latch circuit and said change-over circuit to the initial state.

Claim 9

An input/output device for a programmable controller, comprising: two serial data input terminals A and B, a shift register shifted by a clock signal applied to said clock signal input terminal, a latch circuit connected to a parallel output end of said shift register, a driver for sending out in parallel an output from said latch circuit as external output signals, a receiver for receiving in parallel external input signals and applying said external input signals to parallel input terminals of said shift register, a change-over circuit for switching to any one of the states where a signal applied to said input terminal A is a serial input of said shift register and a serial output of said shift register is sent to said input/output terminal B, and where a signal applied to said input/output terminal B is a serial input of said shift register and a serial output of said shift register is sent to said input/output terminal A, a control circuit for detecting the fixing of the level of a signal applied to said clock signal input terminal for more than a predetermined period of time T1 and for producing a latch signal for said latch circuit, a parallel input read signal for said shift register and an inverted signal for said change-over circuit, and a reset circuit for detecting the fixing of the level of a signal applied to said clock signal input terminal for a predetermined period of time sufficiently longer than said period of time T1 and for returning said latch circuit and said change-over circuit to the initial state.

Claim 10

An input/output device for a programmable controller, comprising: two serial data input terminals A and B, a shift register shifted by a clock signal applied to said clock signal input terminal, a latch circuit connected to a parallel output end of said shift register, a driver for sending out in parallel an output from said latch circuit as external output signals, a receiver for receiving in parallel external input signals and applying said signals to parallel input terminals of said shift register, a change-over circuit for switching to any one of the states where a signal applied to said input terminal A is a serial input of said shift register and a serial output of said shift register is sent to said input/output terminal B, and where a signal applied to said input/output terminal B is a serial input of said shift register and a serial output of said shift register is sent to said input/output terminal A, a control circuit for detecting the fixing of the level of a signal applied to said clock signal input terminal for more than a predetermined period of time and for producing a latch signal for said latch circuit, a parallel input read signal for said shift register and an inverted signal for said change-over circuit, and a delay circuit for slightly delaying a data signal provided at any one of the serial input side and the serial output side of said shift register.

Claim 11

An input/output device for a programmable controller, comprising: two serial data input terminals A and B, a shift register shifted by a clock signal applied to said clock signal input terminal, a latch circuit connected to a parallel output end of said shift register, a driver for sending out in parallel an output from said latch circuit as external output signals, a receiver for receiving in parallel external input signals and applying said signals to parallel input terminals of said shift register, a change-over circuit for switching to any one of the states where a signal applied to said input terminal A is a serial input of said shift register and a serial output of said shift register is sent to said input/output terminal B, and where a signal applied to said input/output terminal B is a serial input of said shift register and a serial output of said shift register is sent to said input/output terminal A, a control circuit for detecting the fixing of the level of a signal applied to said clock signal input terminal for more than a predetermined period of time and for producing a latch signal for said latch circuit, a parallel input read signal for said shift register and an inverted signal for said change-over circuit, and a delay circuit for slightly delaying a data signal provided at any one of the serial input side and the serial output side of said shift register.

Claim 12

An input/output device for programmable controller, comprising: two serial data input/output terminal A and B, a clock signal input terminal, a shift register of (X+1)-bit shifted only in one direction by a clock signal applied to said clock signal input terminal, a latch circuit connected to parallel output ends of X-bits other than 1 bit of said shift register, a driver for sending out in parallel an output of said latch circuit as external output signals, a receiver for receiving in parallel external input signals and applying said signals to parallel input ends of 1 to X-bits of said shift register, a circuit for applying always a high level (H) signal to an input end of (X+1)th bit of said shift register, a parity check circuit connected to parallel output ends of said shift register, a change-over circuit for switching to any one of the states where a signal applied to said input terminal A is a serial input of said shift register and a serial output of said shift register is a serial input of said shift register and a serial output of said shift register is sent to said input/output terminal A, a control circuit for detecting the fixing of the level of a signal applied to said clock signal input terminal for more than a predetermined period of time and for producing a latch signal for said latch circuit, a parallel input read signal for said shift register and an inverted signal for said change-over circuit, and an inhibiting circuit for inhibiting application of said latch signal from said control circuit to said latch circuit when an error signal is sent from said parity check circuit.

Claim 13

An input/output device for programmable controller, comprising: two serial data input/output terminal A and B, a clock signal input terminal, a shift register of (X+1)-bit shifted only in one direction by a clock signal applied to said clock signal input terminal, a latch circuit connected to parallel output ends of X-bits other than 1 bit of said shift register, a driver for sending out in parallel an output of said latch circuit as external output signals, a receiver for receiving in parallel external input signals and applying said signals to parallel input ends of 1 to X-bits of said shift register, a circuit for applying always a high level (H) signal to an input end of (X+1)th bit of said shift register, a parity check circuit connected to parallel output ends of said shift register, a change-over circuit for switching to any one of the states where a signal applied to said input terminal A is a serial input of said shift register and a serial output of said shift register is a serial input of said shift register and a serial output of said shift register is sent to said input/output terminal A, a control circuit for detecting the fixing of the level of a signal applied to said clock signal input terminal for more than a predetermined period of time and for producing a latch signal for said latch circuit, a parallel input read signal for said shift register and an inverted signal for said change-over circuit, and an inhibiting circuit for inhibiting application of said latch signal from said control circuit to said latch circuit when an error signal is sent from said parity check circuit.

Claim 14

An input/output device for a programmable controller, comprising: two serial data input terminals A and B, a shift register shifted by a clock signal applied to said clock signal input terminal, a latch circuit connected to a parallel output end of shift register, a driver for sending in parallel an output from said latch circuit as external output signals, a receiver for receiving in parallel external input signals and applying for receiving in parallel external input signals and applying said signals to parallel input terminals of said shift register, a change-over circuit for switching to any one of the states where a signal applied to said input terminal A is a serial input of said shift register and a serial output of said shift register is sent to said input/output terminal B, and where a signal applied to said input/output terminal B is a serial input of said shift register and a serial output of said shift register is sent to said input/output terminal A, a control circuit for detecting the fixing of the level of a signal applied to said clock signal input terminal for more than a predetermined period of time and for producing a latch signal for said latch circuit, a parallel input read signal for said shift register and an inverted signal for said change-over circuit, a counter for counting clock signals applied to said clock signal input terminal when data is shifted from said serial data input/output terminal A to B and for generating an output signal every time the counted value becomes equal to the number of shifts of said register, and a gate circuit for permitting an application of said latch signal from said control circuit to said latch circuit only when said output signal is sent from said counter.

Claim 15

An input/output device for a programmable controller, comprising: two serial data input terminals A and B, a shift register shifted by a clock signal applied to said clock signal input terminal, a latch circuit connected to a parallel output end of shift register, a driver for sending in parallel an output from said latch circuit as external output signals, a receiver for receiving in parallel external input signals and applying for receiving in parallel external input signals and applying said signals to parallel input terminals of said shift register, a change-over circuit for switching to any one of the states where a signal applied to said input terminal A is a serial input of said shift register and a serial output of said shift register is sent to said input/output terminal B, and where a signal applied to said input/output terminal B is a serial input of said shift register and a serial output of said shift register is sent to said input/output terminal A, a control circuit for detecting the fixing of the level of a signal applied to said clock signal input terminal for more than a predetermined period of time and for producing a latch signal for said latch circuit, a parallel input read signal for said shift register and an inverted signal for said change-over circuit, a counter for counting clock signals applied to said clock signal input terminal when data is shifted from said serial data input/output terminal A to B and for generating an output signal every time the counted value becomes equal to the number of shifts of said register, and a gate circuit for permitting an application of said latch signal from said control circuit to said latch circuit only when said output signal is sent from said counter.