Image sensor

Claim 2

An image sensor for generating multi-bit digital pixel values for analysis in a digital image processor, said image sensor comprising: a single oscillator; a light source for illuminating a target area containing one or more objects; means for generating a modulation reference waveform at a given frequency for modulating the light source, said means comprising said oscillator; detector means for receiving light from the object and generating an information waveform associated therewith; phase detector means for detecting the phase difference between the reference waveform and the information waveform, said phase detector means including: first and second comparator means for converting said reference and information waveforms, respectively, into digital logic level signals; a multi-bit digital counter having a clock input, an enable input, a reset input and an M-bit output; clock means connected between an output of the reference waveform comparator means and the clock input of the counter for driving same at N times the frequency of the reference waveform, wherein N is an integer; control means coupled between the comparator means and the counter, operative to enable the counter to begin counting at the clock frequency upon receipt of an edge of one of the digital logic level signals and to reset the counter upon receipt of a corresponding edge of the other digital logic level signal; and storage means coupled to the counter output and to the control means, operative to store the generated count in the counter whereby the storage means provides a multi-bit digital pixel value representative of characteristics of the target area.

Claim 3

The sensor of claim 1 wherein said clock means comprises: a phase locked-loop frequency multiplier.

Claim 4

The image sensor of claim 1 wherein said light source is amplitude modulated.

Claim 5

The image sensor of claim 1 which further comprises: a second digital counter and an associated second storage means, the second counter being clocked by said clock means and being alternately energized with the other counter by said control means.

Claim 6

The image sensor of claim 4 wherein said control means is operative during one cycle of the reference digital logic level signal to enable one of the counters while causing the contents of the other counter to be stored in its associated storage means and, during a succeeding cycle of the reference digital logic level, being operative to enable the other counter while storing the contents of said one counter in its associated storage means.

Claim 7

The image sensor of claim 5 wherein the control means is further operative to alternately enable the two storage means for transmitting their respective contents to an image processor.

Claim 8

An image sensor for generating three-dimensional image data where each pixel is represented by a multi-bit value, the improvement comprising: a single oscillator; an amplitude modulated laser and a photodetector moving in unison to scan a target area the photodetector generating a series of information waveforms; modulating circuitry, for providing a series of reference waveforms, and comprising said oscillator; phase detector means for detecting the phase difference between the reference and the information waveform, said phase detector including: first and second comparator means for converting said reference and information waveforms into digital logic level signals; a first multi-bit counter having a clock input, an enable input, a reset input and an M bit output; a first latch means having an input connected to the output of the first counter, a store input, an output enable input, and an output; a second multi-bit counter having a clock input, an enable input, a reset input and an M bit output; a second latch means having an input connected to the output of the second counter, a store input, an output enable input and an output; a phase locked loop frequency multiplier having an input connected to the reference comparator means and an output connected to the clock inputs of the first and second counters; and control means coupled between the comparator means and the first counter and latch as well as the second counter and latch, said control means being operative to selectively control the energization of the first counter and transfer the contents of the second counter through the output of the second latch during one cycle of one of the digital logic level signals, and to control the energization of the second counter and transfer the contents of the first counter through the output of the first latch during a succeeding cycle of the digital logic level signal.

Claim 9

An image sensor for generating three-dimensional image data where each pixel is represented by a multi-bit value, the improvement comprising: a single oscillator; an amplitude modulated laser and a photodetector moving in unison to scan a target area the photodetector generating a series of information waveforms; modulating circuitry, for providing a series of reference waveforms, and comprising said oscillator; phase detector means for detecting the phase difference between the reference and the information waveform, said phase detector including: first and second comparator means for converting said reference and information waveforms into digital logic level signals; a first multi-bit counter having a clock input, an enable input, a reset input and an M bit output; a first latch means having an input connected to the output of the first counter, a store input, an output enable input, and an output; a second multi-bit counter having a clock input, an enable input, a reset input and an M bit output; a second latch means having an input connected to the output of the second counter, a store input, an output enable input and an output; a phase locked loop frequency multiplier having an input connected to the reference comparator means and an output connected to the clock inputs of the first and second counters; and control means coupled between the comparator means and the first counter and latch as well as the second counter and latch, said control means being operative to selectively control the energization of the first counter and transfer the contents of the second counter through the output of the second latch during one cycle of one of the digital logic level signals, and to control the energization of the second counter and transfer the contents of the first counter through the output of the first latch during a succeeding cycle of the digital logic level signal.