Coset code generator for computer memory protection

Claim 1

An apparatus for protecting computer memory using coset codes of weight 2 comprising: coding means for receiving a k data bit signal, and for generating an n-k check bit signal of an extended linear (n,k,4) code from said k data bit signal; first generator means for providing an n-k tag bit signal having even weight; second generator means for providing an n-k key bit signal having even weight; addition means, coupled to said coding means and said first and second generator means, for receiving said n-k tag bit signal, and an n-k check bit signal generated from a k data bit signal received by said coding means, and for generating a first sum signal by performing exclusive-OR addition of said n-k tag bit signal to said n-k check bit signal, said first sum signal and said k data bit signal from which said n-k check bit signal is generated being received by said computer memory, said addition means further for receiving said n-k key bit signal, and an n-k check bit signal generated from said k data bit signal read from said memory and received by said coding means, and for generating a second sum signal by performing exclusive-OR addition of said n-k key bit signal to said n-k check bit signal generated from said k data bit signal read from said computer memory and received by said coding means; and testing means, coupled to said addition means, for receiving said first sum signal read from said memory, and for receiving said second sum signal generated by said addition means, and for detecting and indicating a disparity of an even number of bit signals between said first sum signal read from said memory and said second sum signal.

Claim 2

An apparatus for protecting computer memory using coset codes of weight 2 comprising: coding means for receiving a k data bit signal, and for generating an n-k check bit signal of an extended linear (n,k,4) code from said k data bit signal; first generator means for providing an n-k tag bit signal having even weight; second generator means for providing an n-k key bit signal having even weight; addition means, coupled to said coding means and said first and second generator means, for receiving said n-k tag bit signal, and an n-k check bit signal generated from a k data bit signal received by said coding means, and for generating a first sum signal by performing exclusive-OR addition of said n-k tag bit signal to said n-k check bit signal, said first sum signal and said k data bit signal from which said n-k check bit signal is generated being received by said computer memory, said addition means further for receiving said n-k key bit signal, and an n-k check bit signal generated from said k data bit signal read from said memory and received by said coding means, and for generating a second sum signal by performing exclusive-OR addition of said n-k key bit signal to said n-k check bit signal generated from said k data bit signal read from said computer memory and received by said coding means; and testing means, coupled to said addition means, for receiving said first sum signal read from said memory, and for receiving said second sum signal generated by said addition means, and for detecting and indicating a disparity of an even number of bit signals between said first sum signal read from said memory and said second sum signal.

Claim 30

An apparatus for protecting computer memory using coset codes of weight 3 comprising: coding means for receiving a k data bit signal and for generating an n-k check bit signal of an extended linear (n,k,4) code from said k data bit signal; first generator means for providing an n-k tag bit signal chosen from a set of two signals consisting of an all zero n-k bit signal and a fixed but arbitrary n-k bit signal having odd weight, whose n-k bits do not form a column of a correction matrix corresponding to said linear (n,k,4) code; second generator means for providing an n-k key bit signal chosen from said set of two signals; addition means, coupled to said coding means and said first and second generator means, for receiving said n-k tag bit signal, and an n-k check bit signal generated from a k data bit signal received by said coding means, and for generating a first sum signal by performing exclusive-OR addition of said n-k tag bit signal to said n-k check bit signal, said first sum signal, and said k data bit signal from which said n-k check bit signal is generated being received by said computer memory, said addition means further for receiving said n-k key bit signal, and an n-k check bit signal generated from said k data bit signal read from said memory and received by said coding means, and for generating a second sum signal by performing exclusive-OR addition of said n-k key bit signal to said n-k check bit signal generated from said k data bit signal read from said computer memory and received by said coding means; and testing means, coupled to said addition means, for receiving said first sum signal read from said memory and for receiving said second sum signal generated by said addition means, and for detecting and indicating a disparity of an odd number, not less than 3, of bit signals between said first sum signal read from said memory and said second sum signal.

Claim 31

An apparatus for protecting computer memory using coset codes of weight 3 comprising: coding means for receiving a k data bit signal and for generating an n-k check bit signal of an extended linear (n,k,4) code from said k data bit signal; first generator means for providing an n-k tag bit signal chosen from a set of two signals consisting of an all zero n-k bit signal and a fixed but arbitrary n-k bit signal having odd weight, whose n-k bits do not form a column of a correction matrix corresponding to said linear (n,k,4) code; second generator means for providing an n-k key bit signal chosen from said set of two signals; addition means, coupled to said coding means and said first and second generator means, for receiving said n-k tag bit signal, and an n-k check bit signal generated from a k data bit signal received by said coding means, and for generating a first sum signal by performing exclusive-OR addition of said n-k tag bit signal to said n-k check bit signal, said first sum signal, and said k data bit signal from which said n-k check bit signal is generated being received by said computer memory, said addition means further for receiving said n-k key bit signal, and an n-k check bit signal generated from said k data bit signal read from said memory and received by said coding means, and for generating a second sum signal by performing exclusive-OR addition of said n-k key bit signal to said n-k check bit signal generated from said k data bit signal read from said computer memory and received by said coding means; and testing means, coupled to said addition means, for receiving said first sum signal read from said memory and for receiving said second sum signal generated by said addition means, and for detecting and indicating a disparity of an odd number, not less than 3, of bit signals between said first sum signal read from said memory and said second sum signal.