Electronic digital PCM time-division exchange with decentralized architecture

Claim 2

An electronic digital PCM time division exchange connecting subscribers to each other and to said exchange, comprising: a central processing unit; a switching network connected to said central processing unit; and at least one rack connected to said switching network, each rack including: a first PCM bidirectional junction connecting said rack to said switching network; a tri-state circuit connected to said first PCM bidirectional junction; at least one port card, each including at least one port adapted to connect subscribers to said exchange; a second PCM bidirectional junction connecting said at least one port card to said tri-state circuit; and a message processing microcontroller, connected to said at least one port card and to said tri-state circuit and to said first and second PCM bidirectional junctions.

Claim 3

An exchange according to claim 1, wherein said central processing unit includes at least one bidirectional register connected to all of the first PCM bidirectional junctions.

Claim 4

An exchange according to claim 1 wherein said central processing unit includes a random-access memory and a circuit giving direct access to said memory, connected to said switching network by a third bidirectional junction.

Claim 5

An exchange according to claim 1 wherein said message processing microcontroller includes: a computer; a time interval counter; a multiplexer connected to said computer and to said counter; a port selection circuit connected to said multiplexer and to said second PCM bidirectional junction; and a central processing message transmitting circuit connected to said multiplexer and to said first PCM bidirectional junction.

Claim 6

An exchange according to claim 4 wherein said port selection circuit includes: a transmission and reception time selection circuit connected to said multiplexer; a signal transmission circuit connected to said multiplexer and to said second PCM bidirectional junction; and a signal reception circuit connected to said multiplexer and to said second PCM bidirectional junction.

Claim 7

An exchange according to claim 5 wherein said central processing message transmitting circuit includes: a message transmission circuit connected to said multiplexer and to said first PCM bidirectional junction; and a message reception circuit connected to said multiplexer and to said first PCM bidirectional junction.

Claim 8

An exchange according to claim 6 wherein message and signals are exchanged during time intervals, each said rack being assigned a group of time intervals, and wherein said transmission and reception time selection circuit includes: a memory connected to said multiplexer, said memory storing, for each said time interval assigned to said rack, an address of a port card and a port which is to transmit/receive a message; and a first demultiplexer connected to said memory and having an output, for selecting the port card which is to transmit/receive a message.

Claim 9

An exchange according to claim 6 wherein said signal transmission circuit and said message transmission circuit each include: a random access memory connected to said multiplexer; and a parallel-in, serial-out register connected to said random-access memory.

Claim 10

An exchange according to claim 6 wherein said signal reception circuit and said message reception circuit each include: a random access memory connected to said multiplexer; and a serial-in, parallel-out register connected to said random-access memory.

Claim 11

An exchange according to claim 7 wherein each said port card includes: a second demultiplexer connected to said first demultiplexer output; a first register connected to said second demultiplexer and having at least one parallel input and a serial output which is connected to said second PCM bidirectional junction; a second register connected to said second demultiplexer and having at least one parallel output and a serial input which is connected to said second PCM bidirectional junction; and at least one port, each port including: a port transmission/reception selection input connected to said second demultiplxer; a data transmission output connected to said second PCM bidirectional junction; a data reception input connected to said second PCM bidirectional junction; a signal output port connected to said at least one parallel input of said first register; and a signal input port connected to said at least one parallel output of said second register.