US4566099A
Expired / Lapsed
US
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Synchronous clock generator for digital signal multiplex devices
Assignee: Siemens AG
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Filing: 1983-07-01
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Granted: 1986-01-21
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Expires: 2003-07-01
Abstract
Abstract An exemplary embodiment includes a first binary counter whose counting period corresponds to a block length of a pulse frame, a block counter controlled by the first counter, and a logic element for generating working clock signals, wherein the counters are switchable for employment in different multiplex systems and the logic element gates out the working clock signals for different multiplex systems.
Inventors
- 👤 Johann Magerl
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 04:22
CPC Classifications
H; H04; H04J; H04J3/00; H04J3/02; H04J3/04; H04J3/047
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
125 words
A synchronous clock generator for digital signal multiplex devices comprising a first counter whose counting period corresponds to a block length of a pulse frame and which can be set into a prescribed counter reading, a block counter controlled by the first counter, and a logic element for generating working clock signals which logic element is connected to the outputs of the counters, characterized in that change-over means are provided for changing the counting period of at least one of the first counter and the block counter to adapt such counting period selectively to a plurality of respective different multiplexers; and in that the logic element gates out the working clock signals for such respective different multiplexers according to the condition of said changeover means.
Claim 2
Dependent Claim
125 words
A synchronous clock generator for digital signal multiplex devices comprising a first counter whose counting period corresponds to a block length of a pulse frame and which can be set into a prescribed counter reading, a block counter controlled by the first counter, and a logic element for generating working clock signals which logic element is connected to the outputs of the counters, characterized in that change-over means are provided for changing the counting period of at least one of the first counter and the block counter to adapt such counting period selectively to a plurality of respective different multiplexers; and in that the logic element gates out the working clock signals for such respective different multiplexers according to the condition of said changeover means.
Claim 3
Dependent Claim
63 words
A synchronous clock generator according to claim 1, characterized in that a switchable gate is provided as the changeover means for changing over the counting period of the first counter, the inputs of said switchable gate being connected to the outputs of the first counter and the output of said switchable gate being connected to a count setting control of the first counter.
Claim 4
Dependent Claim
124 words
A synchronous clock generator according to claim 2, with a control logic element for the first counter, the first counter having parallel data inputs controlled by the control logic element to control the setting of the first counter to a desired count value, the control logic element having an input to which a synchronizing pulse is supplied for always switching the first counter to the same count value, OR means coupled with the output of the switchable gate and with the input of the control logic element, and having an output connected to the setting control of the first counter for linking the output of the switchable gate and the input of the control logic element with said setting control of said first counter.
Claim 5
Dependent Claim
71 words
A synchronous clock generator according to claim 1, characterized in that a switchable gate is provided as the changeover means and changes over the counting period of the block counter, the inputs of said switchable gate being connected to the outputs of the block counter and OR means coupled with a synchronizing pulse and with said switchable gate and having an output connected to the setting control of the block counter.
Claim 6
Dependent Claim
28 words
A synchronous clock generator according to claim 1, with a synchronously adjustable binary counter being provided for at least one of said first counter and said block counter.
Claim 7
Dependent Claim
27 words
A synchronous clock generator according to claim 2, characterized in that the output of the switchable gate is connected to a carry input of the block counter.
Claim 8
Dependent Claim
31 words
A synchronous clock generator according to claim 1, characterized in that the logic element for generating the working clock signals is switchable according to the desired operation of the multiplexer stage.
Claim 9
Dependent Claim
19 words
A synchronous clock generator according to claim 1, characterized in that said generator is realized in integrated circuit technology.
Claim 10
Dependent Claim
47 words
A synchronous clock generator according to claim 1, characterized in that a first gate element having two outputs is provided, its first output being connected with the setting control of the first counter and its second output being connected to a carry input of the block counter.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-01-20 | 1989-07-22 | 1990-01-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-01-20 | 1993-07-22 | 1994-01-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-01-20 | 1997-07-22 | 1998-01-21 | $7700.00 | Window Closed / Lapsed |