US4564855A
Expired / Lapsed
US
⏱️ 0.0 years remaining
High current PNP transistor forming part of an integrated monolithic circuit
Assignee: Thales SA
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Filing: 1983-03-08
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Granted: 1986-01-14
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Expires: 2003-03-08
Abstract
Abstract A structure associating a high current NPN transistor with a PNP control transistor also able to withstand relatively high currents in an integrated circuit structure. This structure comprises an N + type substrate overlaid by a P type epitaxied layer and a second N type epitaxied layer. The PNP transistor is disposed in the center of a region defined by two successive peripheral isolating walls. The NPN transistor is disposed in the annular zone. In this zone, the N + substrate and the N layer are connected together by a buried N + type layer locally short-circuiting the P type layer along a ring, thus isolating the central part of this layer at the level of the PNP transistor.
Inventors
- 👤 Francois van Zanten
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 07:35
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/60; H10D84/67; H10D84/673; H10W; H10W10/00; H10W10/01; H10W10/031; H10W10/30
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
250 words
A semiconductor structure comprising: (a) an N + substrate; (b) a P layer covering said N + substrate; (c) an N - layer covering said P layer; (d) means for defining a central zone and an annular zone, said defining means including non-intersecting innermost and outermost P + isolating walls passing through said N - layer and at least partially penetrating into said P layer, said central zone being bounded by said innermost P + isolating wall, said annular zone being disposed between said innermost and outermost P + isolating walls; (e) a PNP transistor being disposed in said central zone and having: (i) a P emitter zone formed in said central zone, (ii) an N + base zone formed in said central zone, and (iii) said innermost P + isolating wall providing a collector for said PNP transistor (f) an NPN transistor controlled by said PNP transistor, disposed in said annular zone and including: (i) a P base zone contacting said innermost P + isolating wall, (ii) an N emitter zone disposed on a portion of said P base zone, and (iii) an N + connecting zone contacting both said N + substrate and said N - layer, said N + connecting zone and said N + substrate providing a collector for said NPN transistor, said N + connecting zone being annular in structure to cause a central portion of said P layer to be isolated from portions of said P layer outside said annular N + connecting zone.
Claim 2
Dependent Claim
250 words
A semiconductor structure comprising: (a) an N + substrate; (b) a P layer covering said N + substrate; (c) an N - layer covering said P layer; (d) means for defining a central zone and an annular zone, said defining means including non-intersecting innermost and outermost P + isolating walls passing through said N - layer and at least partially penetrating into said P layer, said central zone being bounded by said innermost P + isolating wall, said annular zone being disposed between said innermost and outermost P + isolating walls; (e) a PNP transistor being disposed in said central zone and having: (i) a P emitter zone formed in said central zone, (ii) an N + base zone formed in said central zone, and (iii) said innermost P + isolating wall providing a collector for said PNP transistor (f) an NPN transistor controlled by said PNP transistor, disposed in said annular zone and including: (i) a P base zone contacting said innermost P + isolating wall, (ii) an N emitter zone disposed on a portion of said P base zone, and (iii) an N + connecting zone contacting both said N + substrate and said N - layer, said N + connecting zone and said N + substrate providing a collector for said NPN transistor, said N + connecting zone being annular in structure to cause a central portion of said P layer to be isolated from portions of said P layer outside said annular N + connecting zone.
Claim 3
Dependent Claim
21 words
A semiconductor structure according to claim 1 wherein said P base zone and said N emitter zone are in interdigitated form.
Claim 4
Dependent Claim
28 words
A semiconductor structure according to claim 1 wherein said PNP transistor further includes an overlapping zone contacting and extending from said innermost isolating wall into said central zone.
Claim 5
Dependent Claim
50 words
A semiconductor structure according to claim 1, wherein a boundary exists between said P layer and said N-layer, and wherein said PNP transistor further includes a buried P layer in said central zone at said boundary, said buried P layer extending into said N - layer and reducing its thickness.
References Cited (Backward Citations)
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US3868722A
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FR2154786A1
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Cited
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Cited
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-01-13 | 1989-07-15 | 1990-01-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-01-13 | 1993-07-15 | 1994-01-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-01-13 | 1997-07-15 | 1998-01-14 | $7700.00 | Window Closed / Lapsed |